Commit Graph

182 Commits

Author SHA1 Message Date
Neil Armstrong
481b5a2424 tests: arm64: add GICv3 ITS test suite
Add a simple ITS driver test allocating 8192 LPIs over 256 DeviceIDS
and 32 EventIDs per DeviceID to exercise the ITS for the MSI/MSI-X
usecase.

The test is set as `build_only: true` and whitelisted to the
fvp_base_revc_2xaemv8a board until the shipped Zephyr QEMU
has the ITS support.
Since `fvp_base_revc_2xaemv8a` needs FIP & BL1 files, test is marked
as `skip: true`.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-09-28 19:45:29 -04:00
Neil Armstrong
0619e96e87 boards: fvp_base_revc_2xaemv8a: reserve HEAP for GICv3 ITS tables
The ITS needs a number of table, so HEAP must be reserved for runtime
allocation (1MiB is a round and convenient value):
- Redistributor:
* 64K table for all redistributors
* 64k for each redistributors
- ITS:
* 4K collection table aligned on 4K
* 4K x 128 device table aligned on 4K

This makes 11x64K to permit all allocations to success.

Note, will need 64K HEAP_MEM per CPUs added.

This doesn't necessarily include the Interrupt Translation Table,
which are 256bytes aligned tables, for reference a 32 ITEs table
needs 256bytes.
With 14x64K HEAP, up to 116 ITT tables of 32 ITEs can be allocated.

A specific HEAP_MEM_POOL_SIZE as been added to arm64_gicv3_its test
for the fvp_base_revc_2xaemv8a board to satisfy all memory allocation
constraints for 256 ITT tables with 32 ITEs allocations.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-09-28 19:45:29 -04:00
Carlo Caione
0f3d2d9230 test: Add arm64_high_addresses test
Latel we have had several failures and regressions due to the setting of
CONFIG_SRAM_BASE_ADDRESS to really high values (over the 4GB boundary).
To try to catch these problems as early as possible we add a build-only
test based on the hello_world_user sample that tries to compile the test
using a combination of CONFIG_SRAM_BASE_ADDRESS and
CONFIG_KERNEL_VM_BASE set to high values in memory.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-08-30 13:38:07 -04:00
Torsten Rasmussen
3d82c7c828 linker: align _image_text_start/end/size linker symbols name
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.

The symbols _image_text_start and _image_text_end sometimes includes
linker/kobject-text.ld. This mean there must be both the regular
__text_start and __text_end symbols for the pure text section, as well
as <group>_start and <group>_end symbols.

The symbols describing the text region which covers more than just the
text section itself will thus be changed to:
_image_text_start -> __text_region_start
_image_text_end   -> __text_region_end

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen
c6aded2dcb linker: align _image_rodata and _image_rom start/end/size linker symbols
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.

The symbols _image_rom_start and _image_rom_end corresponds to the group
ROMABLE_REGION defined in the ld linker scripts.

The symbols _image_rodata_start and _image_rodata_end is not placed as
independent group but covers common-rom.ld, thread-local-storage.ld,
kobject-rom.ld and snippets-rodata.ld.

This commit align those names and prepares for generation of groups in
linker scripts.

The symbols describing the ROMABLE_REGION will be renamed to:
_image_rom_start -> __rom_region_start
_image_rom_end   -> __rom_region_end

The rodata will also use the group symbol notation as:
_image_rodata_start -> __rodata_region_start
_image_rodata_end   -> __rodata_region_end

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen
510d7dbfb6 linker: align _ramfunc_ram/rom_start/size linker symbol names
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each section,
and sometimes even size and LMA start symbols.

Generally, start and end symbols uses the following pattern, as:
Section name:             foo
Section start symbol:     __foo_start
Section end symbol:       __foo_end

However, this pattern is not followed consistently.
To allow for linker script generation and ensure consistent naming of
symbols then the following pattern is introduced consistently to allow
for cleaner linker script generation.
Section name:             foo
Section start symbol:     __foo_start
Section end symbol:       __foo_end
Section size symbol:      __foo_size
Section LMA start symbol: __foo_load_start

This commit aligns the symbols for _ramfunc_ram/rom to other symbols and
in such a way they follow consistent pattern which allows for linker
script and scatter file generation.

The symbols are named according to the section name they describe.
Section name is `ramfunc`

The following symbols are aligned in this commit:
-  _ramfunc_ram_start  -> __ramfunc_start
-  _ramfunc_ram_end    -> __ramfunc_end
-  _ramfunc_ram_size   -> __ramfunc_size
-  _ramfunc_rom_start  -> __ramfunc_load_start

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Daniel Leung
6a58c34aa6 tests: x86/pagetables: limit permission test under demand paging
When demand paging is enabled and not all generic sections are
in physical memory at boot, only tests the permission up to the end
of the pinned section.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-08-26 21:16:22 -04:00
Stephanos Ioannidis
58dbd41b96 tests: arch: arm_no_multithreading: Run on mps3_an547 board
This commit updates the `arm_no_multithreading` test to run on the
recently added `mps3_an547` board.

The `mps3_an547` SoC includes the Cortex-M55 processor which implements
the ARMv8.1-M architecture that is not covered by any of the boards in
the current "allowed platforms" list for this test.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2021-08-25 18:05:01 -04:00
Stephanos Ioannidis
ba7fda70ff tests: arch: arm_no_multithreading: Fix FPSCR validation for ARMv8.1-M
This commit fixes the FPSCR register initialisation validation test
for the ARMv8.1-M architecture.

For ARMv8.1-M, the newly added LTPSIZE field in the FPSCR may always
read the value of 4 when the M-Profile Vector Extension (MVE) is not
implemented or FP context is not active, so we must ignore its value
when validating the FPSCR register initialisation.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2021-08-25 18:05:01 -04:00
Stephanos Ioannidis
06b1501694 tests: arch: arm_thread_swap: Fix FPSCR validation for ARMv8.1-M
This commit fixes the FPSCR register initialisation validation test
for the ARMv8.1-M architecture.

For ARMv8.1-M, the newly added LTPSIZE field in the FPSCR may always
read the value of 4 when the M-Profile Vector Extension (MVE) is not
implemented or FP context is not active, so we must ignore its value
when validating the FPSCR register initialisation.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2021-08-25 18:05:01 -04:00
Torsten Rasmussen
1cccc8a8fe cmake: increase minimal required version to 3.20.0
Move to CMake 3.20.0.

At the Toolchain WG it was decided to move to CMake 3.20.0.

The main reason for increasing CMake version is better toolchain
support.

Better toolchain support is added in the following CMake versions:
- armclang, CMake 3.15
- Intel oneAPI, CMake 3.20
- IAR, CMake 3.15 and 3.20

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-20 09:47:34 +02:00
Bradley Bolen
5accf3596a tests: arm_mem_protect: Add a test for stack pointer manipulation
The Cortex-R architecture uses the threads stack to save context.
However, that is a security hole since a userspace thread could
manipulate the stack pointer before performing a system call and cause
the kernel to write to memory that it should not.  This test will sanity
check that the Cortex-R svc and isr routines do not write to a userspace
supplied stack.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-08-17 06:06:33 -04:00
Ioannis Glaropoulos
453ce7b593 tests: arm: adding a new test-suite for HardFault validation
Adding a new test-suite for HardFault validation,
for Cortex-M Mainline architecture.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos
ab7258a9d5 test: arm: no-multithreading: test triggering PendSV
Add a test case to verify that triggering a
PendSV will lead to a Reserved Exception and
a CPU error, in the no-multithreading case.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos
3843bf655c samples: tfm_integration: adapt DTS overlays for STM32L562 board
Due to changes in flash_layout.h for STM32L562, in the current
TF-M module update, we need to modify the DTS overlay files in
the TF-M samples where the board is supported.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 19:38:35 +02:00
Ioannis Glaropoulos
08510d5b2c tests: arm_thread_swap_tz: increase computational length for secure call
In some platforms, such as the nucleo L552ZE_Q, the hash computation
is done very fast, before the delayed work manages to trigger (and
perform the assert-based validations). Increase the length of the
computations so this race condition can be avoided.

Also, this commit adds some messages in the assert statements for
ease of debugging.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 19:38:35 +02:00
Mahesh Mahadevan
c3567c6f33 tests: arch: arm_irq_vector_table: Update to run on MXRT685
Fix for Issue#35658.
Update the custom vector table to add the OS Event timer
interrupt which is used on RT685 as the kernel system timer

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-07-07 08:25:06 -04:00
Ioannis Glaropoulos
9adf155b62 tests: arm_interrupt: remove redundant test case part
The test case part in test_arm_interrupt, which is
triggering a SysTick IRQ (when SysTick is not used
for system timer implementation), to catch a spurious
interrupt is not really testing what it is designed
for. The reason is that the z_arm_exc_spurious has
be re-designed to be invoked only if the kernel is
built without support for system clock, i.e. with
CONFIG_SYS_CLOCK_EXISTS=n, but this configuration is
not compatible with ZTESTs and is, therefore, never
tested in this test, in any configuration. When the
SysTick is not implemented in the HW, it is not
possible to set the PendSTSET bit, so this is not
possible to execute this part of the test case, anyways.

What we have been catching as an error, here, is the
ASSERT in the sys_clock_isr() weak implementation, but
asserts are verified earlier in this test case, so this
part is really redundant.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-06-24 09:30:35 +02:00
Ioannis Glaropoulos
1a7228a462 tests: add fpu tag the tests which enable FPU and FPU_SHARING options
Introduce the fpu tag to tests that explicitly enable
the FPU and FPU_SHARING Kconfig options. The tag could
be used to run all FPU-related tests in the tree.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-06-22 08:45:41 -04:00
Ioannis Glaropoulos
aa5e2eb720 samples: remove disabling AUDIT_LOG partition in samples with TFM_IPC
The AUDIT_LOG partition cannot be used in TF-M builds
with the IPC mode (CONFIG_TFM_IPC=y); we have added a
relevant dependency for this. So we can cleanup the
CONFIG_TFM_PARTITION_AUDIT_LOG=n from the configuration
files of the samples.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-06-08 04:51:51 -05:00
Øyvind Rønningstad
1929c00643 tests: arm_thread_swap_tz: Enhance testing of FP regs
The existing test puts the same value into all FP registers, runs a
secure service which is then interrupted by a thread that clobbers the
registers.

This patch instead puts different values into each register to test
that each register is restored in the right order.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2021-06-07 15:23:22 +02:00
Anas Nashif
ec5e3017ac boards: up_squared: remove 32bit variant
This board was created for the transition to all 64bit, it is not needed
anymore.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-06-01 14:06:56 -05:00
Ioannis Glaropoulos
ed6729a05e tests: arm: fix name for arm_irq_vector_table test suite
Minor fix to the name for the arm_irq_vector_table
test suite, removing the 'interrupt' from the name.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-05-28 10:41:46 -05:00
Ioannis Glaropoulos
b3b36f69a6 arm: cortex-m: shrink hidden option for null-pointer detection
Shrink the name of the hidden cortex-m option for the
null-pointer dereference detection feature.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-05-26 12:30:05 -05:00
Andy Ross
41e885947e arch/x86: Correct multiboot interpretation when building for EFI
When loaded via EFI, we obviously don't have a multiboot info pointer
available (we might have an EFI system table, but zefi doesn't pass
that through yet).  Don't try to parse the "whatever garbage was in
%rbp" as a multiboot table.

The configuration is a little clumsy, as strictly our EFI kconfig just
says we're "building for" EFI but not that we'll boot that way.  And
tests like arch/x86/info are trying to set CONFIG_MULTIBOOT=n
unconditionally, when it really should be something they detect from
devicetree or wherever.

Fixes #33545

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-05-15 15:30:02 -04:00
Daniel Leung
0a45691aeb tests: x86/pagetables: update test for boot and pinned sections
This updates the test to account for boot and pinned sections.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-05-10 16:00:43 -05:00
Ioannis Glaropoulos
c5b4094cfb modules: tf-m: do not expose TF-M NS interface include directories publicly
Instead of exposing publicly the TF-M NS interface include
directories, we include them when we build relevant projects.
This is required, as the TF-M include directories contains
psa crypto sources that are also provided by the mbedtls
crypto module. The downside of this solution is that the
TF-M includes need to be added explicitly in each application
that uses TF-M APIs.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-05-09 09:59:22 -05:00
Krzysztof Chruscinski
22ae43f0a6 tests: arch: arm: arm_no_multithreading: Add physical platforms
Add 2 nordic boards on which no multithreading test is
passing.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-05-07 14:40:27 +02:00
Ioannis Glaropoulos
89ec3d82ad tests: arm_thread_swap_tz: add tfm tag
Add the tfm tag to the arm_thread_swap_tz test,
since the test is running with TF-M by default.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-05-06 22:17:35 +02:00
Ioannis Glaropoulos
0eb3b3c2c0 tests: arm_thread_swap_tz: correct dt overlays for stm32 boards
Correct thee dt overlays for the STM32 boards, so the Zephyr
image starting address is in accordance with what TF-m expects
it to be.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-05-05 13:00:31 +02:00
Ioannis Glaropoulos
b7c964da48 tests: arm_thread_swap_tz: decrease work delay to ensure test passing
Decrease the submitted work delay, to ensure that the PSA
crypto operation will be preempted when the work fires. The
modification is required for devices with fast crypto
operations. Also minor corrections to the test ase name,
so it is not the same with the other arm_thread_swap test.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-05-05 13:00:31 +02:00
Øyvind Rønningstad
17442cece9 tests: arm: Add arm_thread_swap_tz test
For testing secure->non-secure thread swapping.
This also tests that the FP context is correctly preserved
when calling a secure function.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2021-05-05 13:00:31 +02:00
Øyvind Rønningstad
a2cfb8431d arch: arm: Add code for swapping threads between secure and non-secure
This adds code to swap_helper.S which does special handling of LR when
the interrupt came from secure. The LR value is stored to memory, and
put back into LR when swapping back to the relevant thread.

Also, add special handling of FP state when switching from secure to
non-secure, since we don't know whether the original non-secure thread
(which called a secure service) was using FP registers, so we always
store them, just in case.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2021-05-05 13:00:31 +02:00
Krzysztof Chruscinski
d34a289503 tests: arch: arm: no_multithreading: Limit platforms allowed
When multithreading is off, kernel source files like sem.c (samphore
implementation) are not present in the build. Some platforms by default
fetch modules or drivers that are using multithreading primitives and
because of that fails to compile when multithreading is off.

Limit the test to only qemu platforms since test is arch specific.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-05-04 21:15:36 +02:00
Ioannis Glaropoulos
12025e2620 tests: arm_interrupt: exend test case for FPU SHARING
Extend the stress test of stacking error, to cover
the case of an active FP context.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-05-04 16:47:48 +02:00
Gerard Marull-Paretas
f163bdb280 power: move reboot functionality to os lib
Reboot functionality has nothing to do with PM, so move it out to the
subsys/os folder.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-04-28 20:34:00 -04:00
Ioannis Glaropoulos
13cde704e9 tests: arm_no_multithreading: confirm IRQ index being non-negative
Check that the index returned by the function that looks
for an available IRQ line is non-negative, and do not just
rely on catching this with an ASSERT. That suppresses a
Coverity out-of-bounds warning.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-04-15 15:10:51 -05:00
Nicolas Pitre
0dc7b9ee46 k_current_get(): make it a "const" function
This function always returns the same value for a given thread.
Add the const attribute to it so the compiler won't call it over and
over needlessly each time _current is referenced, making for far more
efficient code.

The __attribute_const__ symbol is used to mimic the Linux equivalent.
We want to make it clear that this is distinct from the const keyword.

Fix the test_x86_cpu_scrubs_regs where the compiler wasn't told that a
bunch of registers are being clobbered as highlighted by this change.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2021-04-14 20:32:05 -04:00
Krzysztof Chruscinski
8bee027ec4 arch: arm: Unconditionally compile IRQ_ZERO_LATENCY flag
Flag was present only when ZLI was enabled. That resulted in additional
ifdefs needed whenever code supports ZLI and non-ZLI mode.

Removed ifdefs, added build assert to irq connections to fail at
compile time if IRQ_ZERO_LATENCY is set but ZLI is disabled. Additional
clean up made which resulted from removing the ifdef.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-04-12 07:33:27 -04:00
Carlo Caione
10b4d7d8e5 test: arm_psci: Move test to arm64_psci directory
To match the parent directory name.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-23 17:02:58 -04:00
Carlo Caione
4e353f0edf test: arm_psci: Fix filter value
The filter value is specified without the leading CONFIG_* so the test
is never executed.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-23 17:02:58 -04:00
Anas Nashif
12b53d121e clock: rename z_timer_cycle_get_32 -> sys_clock_cycle_get_32
This is another API that is being used in all timer drivers and is not
internal to the clock subsystem. Remove the leading z_ and make promote
it to a cross-subsystem API.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-19 11:22:17 -04:00
James Harris
b10428163a kernel: sem: add K_SEM_MAX_LIMIT
Currently there is no way to distinguish between a caller
explicitly asking for a semaphore with a limit that
happens to be `UINT_MAX` and a semaphore that just
has a limit "as large as possible".

Add `K_SEM_MAX_LIMIT`, currently defined to `UINT_MAX`, and akin
to `K_FOREVER` versus just passing some very large wait time.

In addition, the `k_sem_*` APIs were type-confused, where
the internal data structure was `uint32_t`, but the APIs took
and returned `unsigned int`. This changes the underlying data
structure to also use `unsigned int`, as changing the APIs
would be a (potentially) breaking change.

These changes are backwards-compatible, but it is strongly suggested
to take a quick scan for `k_sem_init` and `K_SEM_DEFINE` calls with
`UINT_MAX` (or `UINT32_MAX`) and replace them with `K_SEM_MAX_LIMIT`
where appropriate.

Signed-off-by: James Harris <james.harris@intel.com>
2021-03-05 08:13:53 -06:00
Ioannis Glaropoulos
8e5e719b17 tests: arm: increase idle thread stack size for no-opt test-cases
In the arch/arm test suite there are tests running with
CONFIG_NO_OPTIMIZATIONS enabled, and may require a
larger idle thread stack size.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-03-05 15:03:24 +03:00
Ioannis Glaropoulos
407c76d54f tests: arm thread swap: save and restore callee-saved in subroutine
Temporarily save and restore all callee-saved registers
in the sub-routine, not only the frame pointer, to avoid
errors if compiler chooses to use them in the alternative
thread function. The callee-saved regs are restored after
the alternative thread switches back in.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-03-05 15:03:24 +03:00
Carlo Caione
0f9406277d aarch64: pm_cpu_ops: Introduce pm_cpu_ops subsystem
AArch64 has support for PSCI. This is especially useful for SMP because
PSCI is used to power on the secordary cores.

When the PSCI driver was introduced in Zephyr it was designed to rely on
a very PSCI-centric subsystem / interface.

There are two kinds of problems with this choice:

1. PSCI is only defined for the non-secure world and it is designed to
   boot CPU cores into non-secure state (that means that PSCI is only
   supposed to work if Zephyr is running in non-secure state)

2. There can be other ways or standards used to start / stop a core
   different from PSCI

This patch is trying to fix the original wrong assumption by making the
interface / subsystem a generic one, called 'pm_cpu_ops', and using PSCI
only as an actual driver that is a user of this new interface /
subsystem.

For now the new subsystem is only exposing two methods: cpu_on and
cpu_off, others will probably follow according to the needs.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-04 06:53:19 -05:00
Ioannis Glaropoulos
6a001457d9 tests: arm_interrupt: add test-case for null pointer detection feature
Add a test case for the null pointer dereferencing detection
feature in Cortex-M. The test case is added in arm_interrupt
test suite and the README file is updated accordingly.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-03-03 10:38:29 +01:00
Anas Nashif
0677c7615f tests: arm_thread_swap: fix testsuite setup
Do not declare 2 testsuite, use skip function for test not supported
with userspace instead.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-02-22 14:36:06 -05:00
Ioannis Glaropoulos
ab1600de00 tests: arch: arm: move arm_psci to arm64 directory
arm_psci test suite is specific to ARM64, while
all other test suites in tests/arch/arm directory
are supported in Cortex-M architecture only. We
move arm_psci to arm64 directory, effectively,
separating tests suites for AARCH32 and AARCH64.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-02-19 05:27:31 -06:00
Daniel Leung
2011030600 tests: x86/info: enable testing for userspace
This adds some test cases to test with userspace enabled
to make sure will not be broken.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-02-16 19:08:55 -05:00