interrupt controller, also places its relevant
peripheral sources allowing drivers to use the
DT macros instead of espressif headers.
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Add a macro for encoding interrupt source information: GIRQ number,
GIRQ bit position, GIRQ aggregated NVIC connection, and source
direct NVIC connection.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This change enables A, C, D, E, G, H, I, J, K, and L groups,
and fix gpio interrupt function.
This change also pull (and rename) dt-bindings/irq.h to
dt-bindings/interrupt-controller/ite-intc.h, because it is
chip-specific.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
Use '0xa0' as default priority to be consistent with the V1/V2 and
V3 drivers default priority init.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
For HPET devices, configure it with fixed delivery mode because HPET
timer interrupt is needed to fuel the scheduler for all CPUS.
For all other type of devices, like UART, I2C, GPIO, Ethernet, etc.
configure them as lowest priority delivery mode, in which IO APIC
delivers the interrupt to the processor core that is executing at the
lowest priority among all the processors listed in the specified
destination. In this case, the device drivers can avoid the trouble of
handling repeated interrupts delivered to all CPUS.
Signed-off-by: Zide Chen <zide.chen@intel.com>
The GIC-400 driver currently only supports SPIs because the (32) offset
for the INTIDs is hard-coded in the driver. At the driver level there is
no really difference between PPIs and SPIs so we can easily extend the
driver to support PPIs as well.
This is useful if we want to add support for the ARM Generic Timers that
use INTIDs in the PPI range.
SPI interrupts are in the range [0-987]. PPI interrupts are in the range
[0-15].
This commit adds interrupt 'type' cell to the GIC device tree binding
and changes the 'irq' cell to use interrupt type-specific index, rather
than a linear IRQ number.
The 'type'+'irq (index)' combo is automatically fixed up into a linear
IRQ number by the scripts/dts/gen_defines.py script.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Remove the handcoded multi-level IRQ values in device tree. We now are
able to generate the encoded multi-level IRQ value.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The GIC400 is a common interrupt controller that can be used with the
Cortex A and R series processors. This patch adds basic interrupt
handling for the GIC, but does not handle multiple routing or
priorities.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Add a level 2 interrupt controller for the RV32M1 SoC. This uses the
INTMUX peripheral.
As a first customer, convert the timer driver over to using this,
adding nodes for the LPTMR peripherals. This lets users select the
timer instance they want to use, and what intmux channel they want to
route its interrupt to, using DT overlays.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Mike Scott <mike@foundries.io>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
