The LPI (Locality-specific Peripheral Interrupts) are edge-triggered
message-based interrupts that can use an Interrupt Translation
Service (ITS) to route an interrupt to a specific Redistributor and
connected PE.
This implement the necessary LPI support when an ITS is enabled.
The LPI states are stored in memory-backed tables.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
When affinity routing is enabled for Non-secure state
( GICD_CTLR.ARE_NS is '1'), need to set routing information
for the SPI interrupt.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
In SMP, MPID is mybe not equal to cpu logic ID, so can't
use MPID to get rdist base address from gic_rdists[], this
patch get logic ID from arch_curr_cpu()->id, and
find current CPU's rdist base address from:
gic_rdists[cpu_logic_id]
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add parenthesis for the parameters to avoid the issues if
parameter is an expression but not an immediate value.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add SMP support.
Note: there is still limitation that we rely on NUM CPUs.
And all cpus must be from 0,1,2 and ....
Signed-off-by: Peng Fan <peng.fan@nxp.com>
In _isr_wrapper, the interrupt ID read from the GIC is blindly used to
index into _sw_isr_table, which is only sized based on CONFIG_NUM_IRQ.
It is possible for both GICv2 and GICv3 to return 1023 for a handful
of scenarios, the simplest of which is a level sensitive interrupt
which has subsequently become de-asserted. Borrowing from the Linux
GIC implementation, a read that returns an interrupt ID of 1023 is
simply ignored.
Minor collateral changes to gic.h to group !_ASMLANGUAGE content
together to allow this header to be used in assembler files.
Signed-off-by: Luke Starrett <luke.starrett@gmail.com>
The GIC interrupt controller driver is using a custom init function
called directly from the prep_c function. For consistency move that to
use SYS_INIT.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add api to raise SGI to target cores in affinity level identified
by MPIDR. Currently only EL1S is supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Add basic driver for GIC V3 interrupt controller.
This implementation supports
- distributor, re-distributor and cpu interface initialization
- configuration and handling of SPI, PPI and SGI.
- V2 Legacy mode is not supported and uses system interface.
Current implementation supports GIC secure state only.
All interrupts are routed to Secure EL1 as 'irq' by configuring
them as Group1 Secure.
TODO:
- MPIDR based affinity routing setting.
- percpu redistributor probe
- message based SPI and SGI generation api
- EL1NS support. Legacy mode support.
- LPI/ITS is not supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Convert older DT_INST_ macro use in arm_cmsdk/arm drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the GICD_SGIR register (used for generating software
generated interrupts) field definitions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit fixes the field definition names for `GICD_ICFGR`, which
were incorrectly prefixed with `GICC_`.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The current Generic Interrupt Controller (GIC) driver makes use of the
multi-level interrupt mechanism and `irq_nextlevel` public interface.
This is a less-than-ideal implementation for the following reasons:
1. The GIC is often used as the main interrupt controller for the
Cortex-A and Cortex-R family SoCs and, in this case, it is not a 2nd
level interrupt controller; in fact, it is the root interrupt
controller and therefore should be treated as such.
2. The only reason for using `irq_nextlevel` here is to interface the
architecture implementation to the interrupt controller functions.
Since there is no nesting or multiple instances of an interrupt
controller involved, there is really no point in adding such an
abstraction.
3. 2nd level topology adds many unnecessary abstractions and results
in strange coding artefacts as well as performance penalty due to
additional branching.
This commit refactors the GIC driver interface as follows:
1. Remove the current GIC driver interface based on the multi-level
interrupt mechanism and the `irq_nextlevel` public interface.
2. Define the GIC driver interface in
`include/drivers/interrupt_controller/gic.h` and allow the arch
implementation to directly invoke this interface.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The current GIC driver implementation only supports the GIC-400, which
implements the GICv2 interface.
This commit refactors the GIC driver to support multiple GIC versions
and adds GICv1 interface support (GICv1 and GICv2 interfaces are very
similar).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
