Commit Graph

601 Commits

Author SHA1 Message Date
Torsten Rasmussen
15e834a687 linker: __data_region_start equal to __data_start
Fixes: #38591, #38207, #37861

The commit 65a2de84a9 aligned the data
linker symbol for sections and regions.

The data region symbol start has been placed outside the sections thus
being defined as the address of the region before alignment of the first
section in the data region, usually the `datas` section.

The symbol defining the start address of the data section is after
section alignment.
In most cases the address of the data region start and datas section
start will be identical, but not always.
The data region symbol is a new linker symbol and existing code has
been depending on the old data section start symbol.
Thus, the update to the use of the data region start symbol instead of
data ram start symbol thus results in a different address when the
section is aligned to a different address.

To ensure the original behavior in all cases, the data region start
address is now moved inside the data section.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-09-24 15:13:13 -04:00
Markus Becker
fcb73bd4f6 Tracing: Enable tracing of ISR based on CONFIG_TRACING_ISR
In
https://github.com/zephyrproject-rtos/zephyr/blob/main/arch/arm/core/aarch32/isr_wrapper.S#L90
as well as in
https://github.com/zephyrproject-rtos/zephyr/blob/main/include/arch/arc/v2/irq.h#L93
`CONFIG_TRACING_ISR` is used, here `CONFIG_TRACING` is used. I believe
`CONFIG_TRACING_ISR` would be more correct.

Signed-off-by: Markus Becker <Markus.Becker@tridonic.com>
2021-09-21 19:54:13 -04:00
Torsten Rasmussen
a28830b811 linker: align __itcm_load_start / __dtcm_data_load_start linker symbols
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each section,
and sometimes even size and LMA start symbols.

Generally, start and end symbols uses the following pattern, as:
Section name:             foo
Section start symbol:     __foo_start
Section end symbol:       __foo_end

However, this pattern is not followed consistently.
To allow for linker script generation and ensure consistent naming of
symbols then the following pattern is introduced consistently to allow
for cleaner linker script generation.
Section name:             foo
Section start symbol:     __foo_start
Section end symbol:       __foo_end
Section size symbol:      __foo_size
Section LMA start symbol: __foo_load_start

This commit aligns the symbols for __itcm_load_start and
__dtcm_data_load_start to other symbols and in such a way they follow
consistent pattern which allows for linker script and scatter file
generation.

The symbols are named according to the section name they describe.
Section names are itcm and dtcm.

The following symbols are aligned in this commit:
-  __itcm_rom_start      -> __itcm_load_start
-  __dtcm_data_rom_start -> __dtcm_data_load_start

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen
3d82c7c828 linker: align _image_text_start/end/size linker symbols name
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.

The symbols _image_text_start and _image_text_end sometimes includes
linker/kobject-text.ld. This mean there must be both the regular
__text_start and __text_end symbols for the pure text section, as well
as <group>_start and <group>_end symbols.

The symbols describing the text region which covers more than just the
text section itself will thus be changed to:
_image_text_start -> __text_region_start
_image_text_end   -> __text_region_end

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen
c6aded2dcb linker: align _image_rodata and _image_rom start/end/size linker symbols
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.

The symbols _image_rom_start and _image_rom_end corresponds to the group
ROMABLE_REGION defined in the ld linker scripts.

The symbols _image_rodata_start and _image_rodata_end is not placed as
independent group but covers common-rom.ld, thread-local-storage.ld,
kobject-rom.ld and snippets-rodata.ld.

This commit align those names and prepares for generation of groups in
linker scripts.

The symbols describing the ROMABLE_REGION will be renamed to:
_image_rom_start -> __rom_region_start
_image_rom_end   -> __rom_region_end

The rodata will also use the group symbol notation as:
_image_rodata_start -> __rodata_region_start
_image_rodata_end   -> __rodata_region_end

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen
65a2de84a9 linker: align __data_ram/rom_start/end linker symbol names
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each section,
and sometimes even size and LMA start symbols.

Generally, start and end symbols uses the following pattern, as:
Section name:             foo
Section start symbol:     __foo_start
Section end symbol:       __foo_end

However, this pattern is not followed consistently.
To allow for linker script generation and ensure consistent naming of
symbols then the following pattern is introduced consistently to allow
for cleaner linker script generation.
Section name:             foo
Section start symbol:     __foo_start
Section end symbol:       __foo_end
Section size symbol:      __foo_size
Section LMA start symbol: __foo_load_start

This commit aligns the symbols for _data_ram/rom to other symbols and in
such a way they follow consistent pattern which allows for linker script
and scatter file generation.

The symbols are named according to the section name they describe.
Section name is `data`

A new group named data_region is introduced which instead spans all the
input and output sections that was previously covered by
__data_ram_start, __data_ram_end, and __data_rom_start.

The following symbols are aligned in this commit:
-  __data_ram_start  -> __data_region_start
-  __data_ram_end    -> __data_region_end
-  __data_rom_start  -> __data_region_load_start

The following new symbols are introduced so that the data section is
aligned with other sections:
-  __data_end
-  __data_start
       value identical to __data_region_start but describes start of
       the section.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen
626e16799a linker: removing unused _DATA_IN_ROM
Commit 6b3c5e8bb2 removed the use of
_DATA_IN_ROM but kept the now unused define.

This commit removes the corresponding define which is no longer used.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Jordan Yates
b2dc1fc9fb linker: arm: move IDT_LIST region
Move the IDT_LIST memory region to the location recommended by
`intlist.ld`. The documentation specifies that this region should not
overlap other regions, and there is no guarantee that the area after the
`SRAM` region is not used. The end of the address space is much less
likely to be a valid RAM address.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-08-25 18:08:36 -04:00
Bradley Bolen
03f951c4f6 arch: arm: cortex_r: Move kobject text
Move the kobject text area to be at the beginning of the text section to
match Cortex-M.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-08-17 06:06:33 -04:00
Bradley Bolen
ef50545808 arch: arm: cortex_r: Add userspace support for non-XIP builds
When running non-XIP, userspace threads need to be able to read .text in
order to execute code.  Cortex-R needs to setup an MPU entry to allow
this, but it must be aligned to a power of 2.  The linker scripts for
other archs follow this same pattern of aligning the location counter,
but outside of an input section.  The linker ignores this and places the
next input section at the LMA of the end of the previous input section.
Avoid this problem by make RODATA the last ROM section.  The MPU_ALIGN
can be moved inside the RODATA input section and correctly pad the
entire ROM section out to a power of 2 boundary.

_image_rom_end_order contains the power of 2 alignment which allow the
soc to set the MPU configuration statically based on the size of the ROM
sections instead of having to do it dynamically.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-08-17 06:06:33 -04:00
Bradley Bolen
ff1a5e7858 arch: arm: cortex_r: Add ARCH_EXCEPT macro
With the addition of userspace support, Cortex-R needs to use SVC calls
to handle oops exceptions.  Add that support by defining ARCH_EXCEPT to
do a svc call.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-08-17 06:06:33 -04:00
Bradley Bolen
65dcab81d0 arch: arm: cortex_r: Do not use user stack in svc/isr modes
The user thread cannot be trusted so do not use the stack pointer it
passes in.  Use the thread's privilege stack when in privileged modes to
make sure a user thread does not trick the svc/isr handlers into writing
to memory it should not.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-08-17 06:06:33 -04:00
Phil Erwin
e0bed3b989 arch: arm: cortex_r: Add MPU and USERSPACE support
Use Cortex-M code as a basis for adding MPU support for the Cortex-R.

Signed-off-by: Phil Erwin <phil.erwin@lexmark.com>
2021-08-17 06:06:33 -04:00
Carles Cufi
148005bfe1 arch: aarch32: Add build asserts for IRQ priority range
Figuring out what the lowest possible priority in platforms where
CONFIG_ZERO_LATENCY_IRQS is supported is not possible before the Kconfig
tree is built and resolved. In order to make the user's life easier,
abort the build if IRQ_CONNECT() is called with an invalid (i.e. too
low) priority.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2021-08-09 13:04:28 -04:00
Fabio Baltieri
ef93bbad57 linker: add an initialized DATA_SECTIONS linker location option
Current location options for linker source files includes init and
noinit ram data, but only a noinit ram section. This makes it impossible
for application code to define an initialized RAM output section,
such as with the Z_ITERABLE_SECTION_RAM() helpers.

Adding a DATA_SECTIONS linker source option for this use case.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2021-08-07 20:26:41 -04:00
Martí Bolívar
d1eee6a966 linker: rename DT_REGION_FROM_NODE_STATUS_OKAY
The main motivation is to avoid polluting the all-caps "DT_"
namespace, which within zephyr belongs to devicetree.h.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-08-07 20:24:13 -04:00
Ioannis Glaropoulos
a8d6c14d30 arm: cortex-m: clean up some more hard-coded constants in swap_helper
Clean up a few more hard-coded constants
in swap_helper.S and replace them with
CMSIS-like defines in cpu.h. No behavioral
changes in this commit.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos
03c4bcd920 arm: use BASEPRI_MAX instead of BASEPRI to mask interrupts
When locking interrupt in a critical session, it is
safer to do MSR BASEPRI_MAX instead of BASEPRI. The
rationale is that when writing to BASEPRI_MAX, the
writing is conditional, and is only applied if the
change is to a higher priority level. This commit
replaces BASEPRI with BASEPRI_MAX in operations that
aim to lock some specific interrupts:
- irq_lock()
- masking out PendSV
So, for example, it is not possible to actually
unmask any interrupts by doing an irq_lock operation.
The commit does not introduce behavioral changes.
However, it makes irq_lock() more robust against
future changes to the IRQ locking mechanism.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Bradley Bolen
50a6dafdc5 arch: aarch32: cortex_m/r: Add arch helper function
Create z_arm_thread_is_user_mode to abstract the implementation
differences between Cortex-M and R to determine if the current thread is
in user or kernel mode.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-07-28 21:08:09 -04:00
Øyvind Rønningstad
382bbacb0a tfm: Put saving of FPU context into its own file so it can be reused
Also, this eases readability.

The new API can be used any time all FP registers must be manually
saved and restored for an operation.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2021-06-07 15:23:22 +02:00
Marek Pieta
94cc9a9bdb arch: arm: Fix build warning
Change fixes a build warning related to attribute ignored in
declaration of struct. The __packed attribute is removed.

Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
2021-05-26 11:17:45 -05:00
Bradley Bolen
3b6707f140 arch: arm: aarch32: Use mpu headers from common aarch32 location
The mpu headers moved in order to support the Cortex-R mpu in later
commits.  Use the new locations.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-05-06 19:39:09 +02:00
Bradley Bolen
2076131543 arch: arm: aarch32: mpu: Move mpu header files up one level
Prepare for Cortex-R MPU support by moving the MPU headers to the
aarch32 common directory.  Add compat headers to ease the transition for
the Cortex-M external modules.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-05-06 19:39:09 +02:00
Øyvind Rønningstad
a2cfb8431d arch: arm: Add code for swapping threads between secure and non-secure
This adds code to swap_helper.S which does special handling of LR when
the interrupt came from secure. The LR value is stored to memory, and
put back into LR when swapping back to the relevant thread.

Also, add special handling of FP state when switching from secure to
non-secure, since we don't know whether the original non-secure thread
(which called a secure service) was using FP registers, so we always
store them, just in case.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2021-05-05 13:00:31 +02:00
Jordan Yates
a0909ac00b linker: stm32f0: move ram vector table to snippets
Move the STM32F0 specific ram vector table sections into a dedicated
linker snippet included by the new `SRAM_VECTOR_TABLE` symbol.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-04-30 15:16:02 +02:00
Jordan Yates
318ee971c5 boards: stm32f0: explicit RAM vector table control
Add a new Kconfig symbol that explicitly controls whether the vector
table should be placed in RAM. This eliminates the side effect of
`IS_BOOTLOADER` controlling vector table location. Making the condition
a positive assertion also allows the config to be used in CMakeLists
conditions (`zephyr_linker_sources_ifdef()`, etc).

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-04-30 15:16:02 +02:00
Daniel Leung
1117169980 kernel: generate placeholders for kobj tables before final build
Due to the use of gperf to generate hash table for kobjects,
the addresses of these kobjects cannot change during the last
few phases of linking (especially between zephyr_prebuilt.elf
and zephyr.elf). Because of this, the gperf generated data
needs to be placed at the end of memory to avoid pushing symbols
around in memory. This prevents moving these generated blocks
to earlier sections, for example, pinned data section needed
for demand paging. So create placeholders for use in
intermediate linking to reserve space for these generated blocks.
Due to uncertainty on the size of these blocks, more space is
being reserved which could result in wasted space. Though, this
retains the use of hash table for faster lookup.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-04-27 13:32:00 -04:00
Mario Jaun
43ef9013a8 arch: arm: add define REGION_RAM_NOCACHE_ATTR
Add a define for non cachaeable RAM for MPU region definitions.

Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
2021-04-27 14:16:35 +02:00
Mario Jaun
100227cc85 linker: arm: add SRAM3/4 linker section
Add a linker section for SRAM3/4 if it is enabled in the device tree.

Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
2021-04-27 14:16:35 +02:00
Jordan Yates
18d3f4dc36 linker: cc13x2_cc26x2: CCFG to linker snippets
Move the TI_CCFG linker section code into a dedicated snippet in the soc
directory.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-04-15 12:25:55 +02:00
Jordan Yates
8fb37b94fd linker: cc13x2_cc26x2: CCFG registers as partition
Define the FLASH_CCFG memory region from a devicetree partition instead
of from math in the linker file. Removing the special math case results
in the FLASH_CCFG region overlapping the FLASH region, but the linker
accepts this until the FLASH region actually starts placing variables
in the FLASH_CCFG region.

As a result, applications that don't fit in (FLASH_SIZE - 88) bytes will
still fail to link, just with an overlapping memory region error instead
of an overflow error.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-04-15 12:25:55 +02:00
Jordan Yates
a4150c0483 linker: stm32wb: move IPC RAM definition to DT
Move the definition of the two IPC RAM blocks from `#define`'s in family
linker scripts to proper devicetree nodes. Use the devicetree nodes to
generate the memory regions.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-04-15 12:25:55 +02:00
Jordan Yates
ddc25b4bdf linker: aarch32: simplify memory region generation
Simplify the linker script by using the helper macros introduced in
<linker/devicetree_regions.h>. The conditional checks on the Kconfig
symbols are discarded as their default values are typically set via
the status="okay" property of the nodes, and hence the behaviour doesn't
change.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-04-15 12:25:55 +02:00
Krzysztof Chruscinski
8bee027ec4 arch: arm: Unconditionally compile IRQ_ZERO_LATENCY flag
Flag was present only when ZLI was enabled. That resulted in additional
ifdefs needed whenever code supports ZLI and non-ZLI mode.

Removed ifdefs, added build assert to irq connections to fail at
compile time if IRQ_ZERO_LATENCY is set but ZLI is disabled. Additional
clean up made which resulted from removing the ifdef.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-04-12 07:33:27 -04:00
Flavio Ceolin
95cd021cea arch: arm: Fix 14.4 guideline violation
The controlling expression of an if statement has to be an
essentially boolean type.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-04-06 10:25:24 -04:00
Carlo Caione
3539c2fbb3 arm/arm64: Make ARM64 a standalone architecture
Split ARM and ARM64 architectures.

Details:

- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
  (arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
  boards/bcm_vk/viper directory

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-31 10:34:33 -05:00
Carlo Caione
d4066dae83 aarch64: Rework linker script for better MMU support
In acda9bf9ce new macros were introduced to support a virtual memory
map. Adjust these macros also for AArch64. This also fixes a problem
when building Zephyr when CONFIG_KERNEL_VM_BASE is not the same as
CONFIG_SRAM_BASE_ADDRESS

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-26 08:24:50 -04:00
Kumar Gala
520ebe4d76 arch: arm: remove compat headers
These compat headers have been moved since at least v2.4.0 release so we
can now remove them.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-03-25 16:40:25 +01:00
Carlo Caione
807991e15f AArch64: Do not use CONFIG_GEN_PRIV_STACKS
We are setting CONFIG_GEN_PRIV_STACKS when AArch64 actually uses a
statically allocated privileged stack.

This error was not captured by the tests because we only verify whether
a read/write to a privileged stack is failing, but it can fail for a lot
of reasons including when the pointer to the privileged stack is not
initialized at all, like in this case.

With this patch we deselect CONFIG_GEN_PRIV_STACKS and we fix the
mem_protect/userspace test to correctly probe the privileged stack.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-25 07:23:19 -04:00
Kumar Gala
95e4b3eb2c arch: arm: Add initial support for Cortex-M55 Core
Add initial support for the Cortex-M55 Core which is an implementation
of the Armv8.1-M mainline architecture and includes support for the
M‑profile Vector Extension (MVE).

The support is based on the Cortex-M33 support that already exists in
Zephyr.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-03-23 13:13:32 -05:00
Anas Nashif
12b53d121e clock: rename z_timer_cycle_get_32 -> sys_clock_cycle_get_32
This is another API that is being used in all timer drivers and is not
internal to the clock subsystem. Remove the leading z_ and make promote
it to a cross-subsystem API.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-19 11:22:17 -04:00
Carlo Caione
ec70b2bc7a aarch64: userspace: Add support for page tables swapping
Introduce the necessary routines to have the user thread stack correctly
mapped and the functions to swap page tables on context switch.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-18 19:33:59 -04:00
Carles Cufi
59a51f0e09 debug: Clean up thread awareness data sections
There's no need to duplicate the linker section for each architecture.
Instead, move the section declaration to common-rom.ld.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2021-03-17 14:43:01 -05:00
Carlo Caione
a010651c65 aarch64: mmu: Add initial support for memory domains
Introduce the basic support code for memory domains. To each domain
is associated a top page table which is a copy of the global kernel
one. When a partition is added, corresponding memory range is made
private before its mapping is adjusted.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2021-03-16 08:43:19 -04:00
Peng Fan
b4f5b9e237 aarch64: reset: initialize CNTFRQ_EL0 in the highest EL
Can only be written at the highest Exception level implemented.
For example, if EL3 is the highest implemented Exception level,
CNTFRQ_EL0 can only be written at EL3.

Also move z_arm64_el_highest_plat_init to be called when is_el_highest

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-03-11 12:24:18 +01:00
Carlo Caione
dacd176991 aarch64: userspace: Implement syscalls
This patch adds the code managing the syscalls. The privileged stack
is setup before jumping into the real syscall.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-10 14:52:50 -05:00
Carlo Caione
6978160427 aarch64: userspace: Introduce arch_is_user_context
The arch_is_user_context() function is relying on the content of the
tpidrro_el0 register to determine whether we are in user context or not.

This register is set to '1' when in EL1 and set back to '0' when user
threads are running in userspace.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-10 14:52:50 -05:00
Carlo Caione
c559591380 aarch64: stack: Rework memory stack allocations
Introduce the necessary macros and defines to have the stack regions
correctly aligned and sized.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-10 14:52:50 -05:00
Peng Fan
a2ea20dd6d arch: arm: aarch64: add SMP support
With timer/gic/cache added, we could add the SMP support.
Bringup cores

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-03-06 07:36:37 -05:00
Peng Fan
cfc7673c28 aarch64: add arch_curr_cpu
Following other ARCHs, add arch_curr_cpu in arch_inlines.h

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-03-06 07:36:37 -05:00