To keep the generic DMA device name as defined
in the dma framework config, renamed paxdma device
label to "DMA_1".
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Update register addresses and NVIC/GIC interrupt numbers
according to the latest viper RTL version.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
The compatible for the ARMv8 timer should have been arm,armv8-timer and
not arm,arm-timer. The dts binding file name was correct, just the
compatible was wrong. Rename dts, binding, and associated code to use
arm,armv8-timer.
Fixes#31946
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The arm64 timer node has not reg property and thus shouldn't be a
child of the SoC MMIO node. Move the arm,arm-timer up one level
to address this warning.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add tx/rx pl330 channel IDs for the iProc PCIe client usage.
pl330 channel 0 is allocated for Tx DMA (Device to Host write) and
pl330 channel 1 is allocated for Rx DMA (Host to Device read).
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
MSI-X PVM feature requires snoop interrupt for tracking configuration
space register (msix_cap) update and PCIe PMON lite interrupt for
tracking MSI-X table update. Add both the interrupts for Viper M7 DT.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
In aarch64 DTs, priority and flags cells have been swapped,
fix the same.
Correct interrupt property per the GIC binding document
looks like:
interrupts = <irq_type irq_num irq_flags irq_priority>;
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add initial support for Broadcom Viper SoC.
It has ARM Cortex-M7 and Cortex-A72 cores.
Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
