Commit Graph

83980 Commits

Author SHA1 Message Date
YuLong Yao
8a29fb5fa5 samples: subsys: settings: add esp32s3_luatos_core
add conf file for esp32c3_luatos_core board

Signed-off-by: YuLong Yao <feilongphone@gmail.com>
2023-09-15 14:17:50 +02:00
YuLong Yao
10d66c4f63 samples: subsys: nvs: add esp32s3_luatos_core
add conf file for esp32c3_luatos_core board

Signed-off-by: YuLong Yao <feilongphone@gmail.com>
2023-09-15 14:17:50 +02:00
YuLong Yao
8704419126 Samples: net: wifi: add esp32c3_luatos_core board
add overlay and conf for esp32c3_luatos_core board

Signed-off-by: YuLong Yao <feilongphone@gmail.com>
2023-09-15 14:17:50 +02:00
YuLong Yao
b9d3909589 boards: riscv: Introduce esp32c3_luatos_core board
ESP32C3 LuatOS core is a dev board with esp32-c3.
It has similar functions to esp32c3 devkitm, but smaller in size.

Signed-off-by: YuLong Yao <feilongphone@gmail.com>
2023-09-15 14:17:50 +02:00
Fabio Baltieri
21a36f6063 manifest: update hal_ti
Update hal_ti to include a build error fix.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-09-15 13:27:38 +02:00
Pieter De Gendt
a6d81591a2 tests: gen_inc_file: Add tests for optional offset/length
Add tests to validate the optional offset/length arguments for the
file2hex python script.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2023-09-15 13:23:30 +02:00
Pieter De Gendt
ae8c72444e scripts: build: file2hex: Add optional offset and length parameters
Add optional offset and length parameters to generate partial hex files.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2023-09-15 13:23:30 +02:00
Benjamin Cabé
6be960ae71 drivers: rtc: drop printk statement from RTC Shell
Remove a printk forgotten in rtc get command.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2023-09-15 12:11:24 +01:00
Alberto Escolar Piedras
5029922384 mbedtls module: Fix for other POSIX arch boards
Instead of detecting that we are in a native/POSIX arch based
board by checking for each board specifically,
let checks for the architecture.
In that way other boards (like the upcoming nrf53_bsim ones)
will also work.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-09-15 12:58:00 +02:00
Pieter De Gendt
b255182a13 tests: modules: Add nanopb tests
Add test cases for nanopb for simple and nested complex messages.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2023-09-15 12:57:40 +02:00
Pieter De Gendt
0357b4d4f5 modules: nanopb: Add helper function to generate sources
Introduce a helper function zephyr_nanopb_sources to generate
source files and add these to a target.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2023-09-15 12:57:40 +02:00
Pieter De Gendt
07a898bbdf MAINTAINERS: nanopb: Update status to maintained
Change my collaborator role to maintainer and add test files entry.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2023-09-15 12:57:40 +02:00
Carlo Caione
e4a125b6a4 dt: Make zephyr,memory-attr a capabilities bitmask
This is the final step in making the `zephyr,memory-attr` property
actually useful.

The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.

With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.

The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).

For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_VOLATILE |
			       DT_MEM_NON_CACHEABLE |
			       DT_MEM_OOO )>;
   };

The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-region = "NOCACHE_REGION";
       zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
   };

See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).

The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
			       DT_MEM_SW_ALLOCATABLE )>;
   };

Or maybe we can leverage the property to specify some alignment
requirements for the region:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_CACHEABLE |
			       DT_MEM_SW_ALIGN(32) )>;
   };

The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).

When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`

Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory  region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-09-15 12:46:54 +02:00
Dmytro Firsov
7f04c352c1 snippets: xen_dom0: add support for Renesas R-Car Gen3 boards
Renesas rcar_h3ulcb_ca57 and rcar_salvator_xs_m3 boards support recently
was added to Zephyr mainline. Add Xen control domain guest support for
them via xen_dom0 snippet extention.

Note: please pay attetion to overlay nodes and comments in case of any
issues on your setup.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2023-09-15 11:15:00 +01:00
Dmytro Firsov
5207c6f3f9 snippets: add virtual Xen dom0 snippet support
Zephyr snippets allow to apply pre-defined build configuration and
extentions to your build0. It is made by applying generic snippet
conf/device-tree changes and may be extended with platform-specific
files.

It looks like great approach for convertion Zephyr OS build to Xen
control domain on different boards, as it requires Kconfig changes
and board device tree changes (configuration for memory node, hypervisor
console, grant table region etc).

Please note, that Xen hypervisor passes all selected parameters via
domain device-tree, but Zephyr does not use it in runtime. So, user
should keep values in board overlays in sync with real Xen values.

Add example and docs for converting qemu_cortex_a53 board to Xen
Domain-0 guest. This approach might be used for other boards, where
Zephyr Dom0 is needed.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2023-09-15 11:15:00 +01:00
Dmytro Firsov
3942e3ccff xen: add helper functions for Xen domain memory management
Add wrapper functions for Xen memory managment hypercall. They can be
used for unprivilaged Zephyr guest initialization and for domain
management, when Zephyr is used as Xen Domain 0.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2023-09-15 11:15:00 +01:00
Dmytro Firsov
74b271bc2a xen: change HVM functions signature to run it for other domains
This commit adds possibility to call hypervisor HVM parameter functions
for specified domain (instead of only DOMID_SELF). It is needed for
configuring domains, that were created from Zephyr control domain.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2023-09-15 11:15:00 +01:00
Dmytro Firsov
3581527b53 xen: implement Xen domain control interface
Add Xen domctl API implementation for Zephyr as control domain.

Previously Zephyr OS was used as unprivileged Xen domain (Domain-U),
but it also can be used as lightweight Xen control domain (Domain-0).
To implement such fuctionality additional Xen interfaces are needed.
One of them is Xen domain controls (domctls) - it allows to create,
configure and manage Xen domains.

Also, used it as a possibility to update files copyright and licenses
identifiers in touched files.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2023-09-15 11:15:00 +01:00
Dmytro Firsov
0c69913eae xen: dom0: update Xen public headers for running Zephyr as Dom0
Xen public headers are added to Zephyr kernel partially, so we need
to update them for new features implementation.

Further implementation of Xen domains configuration and memory
management requires dedicated Xen public headers inside Zephyr kernel.
It will be used for add Zephyr OS Xen Domain-0 funtionalities.

Update existent and add new required public headers from Xen 4.17.0
release.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2023-09-15 11:15:00 +01:00
Dmytro Firsov
5852dd2b1a xen: events: add event channel allocation for domain-0
This commit adds interface for evtchn allocation that can be used by
privilaged domain. Domain 0 can specify both dom and remote_dom
parameters for hypercall, where in others domains dom should be always
DOMID_SELF. It is needed for creating pre-defined channels during
domain setup in Zephyr Dom0.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2023-09-15 11:15:00 +01:00
Dmytro Firsov
c9d2fb7d40 xen: refactor Xen hypervisor Kconfig options
Xen-related Kconfig options were highly dependand on BOARD/SOC xenvm.
It is not correct because Xen support may be used on any board and SoC.

So, Kconfig structure was refactored, now CONFIG_XEN is located in
arch/ directory (same as in Linux kernel) and can be selected for
any Cortex-A arm64 setup (no other platforms are currently supported).

Also remove confusion in Domain 0 naming: Domain-0, initial domain,
Dom0, privileged domain etc. Now all options related to Xen Domain 0
will be controlled by CONFIG_XEN_DOM0.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2023-09-15 11:15:00 +01:00
Mykola Kvach
66dfe7b99a dts: bindings: xen: add xen,xen.yaml file
Add yaml file for 'xen,xen', because without it an appropriate
'CONFIG_DT_HAS_XEN_XEN_ENABLED' isn't generated.

It will be used for checking Xen support on current setup, instead of
checking if it is BOARD/SOC "xenvm" (which is not correct for Domain-0
configurations).

Remove xen,xen-4.15.yaml at all, because it isn't necessary to have
yaml for some specific Xen version.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2023-09-15 11:15:00 +01:00
Dmytro Firsov
40fe36669c tests: kernel: exclude xenvm from device tests
Zephyr device and device.pm tests uses device tree fragments applied
to main board device trees. For xenvm they have conflicting
address/size cells definition with board DT. It leads to CI and test
issues during build (xenvm has 0x2 cells, tests have 0x1).

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2023-09-15 11:15:00 +01:00
Mykola Kvach
62fd5ab3e1 drivers: xen: gnttab: do Xen node mapping inside driver
Move memory mapping of Xen node to Grant Table driver system init
function. After moving mapping we don't need anymore records of
xen-xen node into 'mmu_regions' array, so they were deleted from
all SoCs: Rcar Gen3/Gen4 and XenVM.

We need at least 16M of virtual address space to map memory of Xen
node, so the virtual memory sized has been increased to 32 MB, it
should be enough for basic use-cases and mapping of 16M mem region
of Xen node.

Unfortunately, after moving we also need to increase number of XLAT
tables. The previous code was more efficient if we talking about
usage of XLAT tables, because it mapped grant tables using a higher-
order table that allows mapping blocks of 2MB. And after the changes
is maps every 4KB page, so we need more XLAT tables.

Increase number of grant frames, it is needed to sync stage 1 and stage 2
memory mappings, previously we map only one page on stage 2 and further
usage of unmap regions can cause MMU translation errors.

Perform mapping stage 1 before mapping for stage 2 (add to physmap),
because right after stage 1 we can try to access memory and if it is
unmap in stage 2, error will be received during translation.

Note: Xen Grant Table driver doesn't use Zephyr Device Model.

Authored-by: Mykola Kvach <mykola_kvach@epam.com>
Co-authored-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
2023-09-15 11:15:00 +01:00
Carles Cufi
ef041c6b98 modules: acpica: Fix header inclusion issue
After 79d0bf39b8 was merged, the inclusion
of <zephyr/acpi/acpi.h> with CONFIG_ACPI=n caused a build failure because
<acpica/source/include/acpi.h> could no longer be included due to the
inlcude path not being injected anymore.

Fix this by guarding the header inclusion when CONFIG_ACPI
is not set.

Fixes #62679.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2023-09-15 05:41:04 -04:00
Vinayak Kariappa Chettimada
d42d14e392 Bluetooth: Controller: Fix missing lazy calculation for Central ISO
Fix missing lazy calculation when using ticker interface
required for Central CIS create.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2023-09-15 09:27:37 +02:00
Vinayak Kariappa Chettimada
1291e4b686 Bluetooth: Controller: Fix initialization of lazy_active
Fix initialization of CIS lazy_active event count used when
first CIS event is active. Now initialization for first and
any subsequent CISes made active.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2023-09-15 09:27:37 +02:00
Vinayak Kariappa Chettimada
afd48e03d0 Bluetooth: Controller: Minor clean up of redundant initialization
Minor clean up of redundant initialization.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2023-09-15 09:27:37 +02:00
Gerard Marull-Paretas
6ee650a917 toolchain: do not allow including toolchain-specific headers
Toolchain utilities need to be used through the <zephyr/toolchain.h>
parent header, where the right header is chosen.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-15 09:27:30 +02:00
Gerard Marull-Paretas
aaeb0a672e toolchain: only include <zephyr/toolchain.h>
It is wrong to use toolchain-specific header files.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-15 09:27:30 +02:00
Théo Battrel
e5de0b6824 west: fix wrong zsh completion
The subcommand 'spdx' was suggesting '-d' for SPDX output directory
instead of '-s'.

Signed-off-by: Théo Battrel <theo.util@protonmail.ch>
2023-09-15 09:27:20 +02:00
Théo Battrel
4dc648642f west: Fix a typo in the fish completion script
In the `help` command, 'status' was written 'statue'.

Signed-off-by: Théo Battrel <theo.util@protonmail.ch>
2023-09-15 09:27:20 +02:00
Mahesh Rao
dec80da4c0 samples: subsys: shell_module: Add support for intel_socfpga_agilex series
Add sip_svc shell support to intel_socfpga_agilex_socdk
and intel_socfpga_agilex5_socdk boards.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
5a7552bce8 samples: sip_svc: Add support for intel_socfpga_agilex5_socdk
Add support for intel_socfpga_agilex5_socdk for
sip_svc sample application.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
80a863f947 tests: sip_svc: Add a stress test for sip_svc subsystem
Add a stress test for sip_svc subsystem using
INTEL SOCFPGA AGILEX platform.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
1a4e5dff5d dts: arm64: intel: Add support for sip_svc for agilex5
Add support for SiP SVC driver for intel_socfpga_agilex5_socdk.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
a57a90feb4 subsystem: sip_svc: Reduce the max timeout to 1 second.
Reduce the max timeout for shell to 1 second.
Change the sip_svc open shell function to take millisecond as timeout
argument.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
c13466974e subsystem: sip_svc: Use atomic variable for locking in singly open system
Use atomic variable for singly open system.
Add k_timer_stop() for sip_svc open timer().

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
97f9d3c60b subsystem: sip_svc: Initialize clients structure after allocation
Initialize client structure after memory allocation.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
817f44f714 subsystem: sip_svc: Change polling delay to micro seconds
Change polling delay to use microseconds.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
7b2e82ecc7 subsystem: sip_svc: Check the number of clients as part of build
Check number of clients as part of build.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
0993bce77d subsystem: sip_svc: Increase stack size for sip_svc thread
Increase sip_svc thread stack size to 4096.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
f816f787e2 drivers: sip_svc: sip_smc_intel_socfpga: Log execution time
Log execution time for each svc call.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
629a6bf106 drivers: sip_svc: sip_smc_intel_socfpga: Fix type error
Fix typo error in code.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
17cfcaea13 driver: sip_svc: Add RSU_UPDATE_ADDR function id
Add RSU UPDATE function id in sip_svc to set the RSU UPDATE
ADDRESS in sip_svc_v2 for Intel Agilex SOCFPGA platform.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Mahesh Rao
c5d224abb6 dts: arm64: intel: Change compat string for Intel Agilex SiP SMC driver.
Change compat string from intel,agilex-socfpga-sip-smc
to intel,socfpga-agilex-sip-smc for Intel AGILEX SOC FPGA sip smc driver.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
Daniel Leung
3441c70117 tests: mem_protect/mem_protect: reuse child thread and stack
This reuses the child_thread variable and child_stack acorss
test suites.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-09-15 09:26:26 +02:00
Daniel Leung
4bebb65491 tests: mem_protect/mem_protect: fix number of kobjects to test
In test_kobject_perm_error, there are 13 kobjects to test but
the loop only do 12. So amend the code to test all 13 kobjects.

Also remove the parameter of tid to child thread as the child
thread is not using it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-09-15 09:26:26 +02:00
Florian La Roche
79d0bf39b8 modules/acpica: CMakeLists.txt: move conditional to beginning of file
Move the conditional compile of CONFIG_ACPI to the beginning of the file
as we currently add compiler include paths to all projects even if
CONFIG_ACPI is not set.

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
2023-09-15 09:26:14 +02:00
Martin Jäger
6d67a56d5b drivers: serial: uart_nrfx_uart: fix NRFX_WAIT_FOR result type
This macro expects a bool variable to store the result.

Signed-off-by: Martin Jäger <martin@libre.solar>
2023-09-14 16:51:32 -05:00