Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
QEMU does its dynamic instruction translation in 4096-byte-sized chunks.
Therefore it doesn't vet PMP access for each instruction prefetch but
for the whole "page" at once. If the end of the ROM area lands in the
middle of such a page with a corresponding PMP entry then any instruction
access within that page will fault even if it is located in the PMP
mapped portion.
To work around this QEMU peculiarity, we simply align the end of the ROM
area to a page boundary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Overall diffstat with the new PMP code in place:
18 files changed, 866 insertions(+), 1372 deletions(-)
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The idea here is to compute the PMP register set on demand i.e. upon
scheduling in the affected threads, and only if changes occurred.
A simple sequence number is used to stay in sync with the latest update.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Stackguard uses the PMP to prevents many types of stack overflow by
making any access to the bottom stack area raise a CPU exception. Each
thread has its set of precomputed PMP entries and those are written to
PMP registers at context switch time.
This is the code to set it up. It will be connected later.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Added macro SHELL_SUBCMD_SET_CREATE which creates a set of subcommands.
SHELL_SUBCMD_ADD and SHELL_SUBCMD_COND_ADD can be used from any file to
add command to the set. This approach allows to have subcommands added
from multiple files.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Enabled DTLS session cache for support session resume.
Fixed LwM2M queue mode for close connection and reconnect automatically.
Re-connect will do Registration update before it send queued data.
Session resume is helping a case when NAT change address and cause less
network traffic.
Signed-off-by: Juha Heiskanen <juha.heiskanen@nordicsemi.no>
sparse complains about cbprintf incompatible callback type and
incorrect size of struct __va_list. Add exceptions to silence those
errors.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Two TLS features developed in parallel resulted in the same option
number being assigned to two options. In this case give preference to
TLS_NATIVE, since it was longer in the tree.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Introduce TLS socket options, which allow to configure session caching
on a socket.
The cache can be enabled on a socket with TLS_SESSION_CACHE option.
Once cache is enabled on a socket, the session will be stored for re-use
after a sucessfull handshake. If a socket is attempting to connect to a
host for which session is stored, the session will be resumed and mbed
TLS will attempt to use a simplified handshake procedure.
The server-side management of sessions is fully controlled by mbed TLS
after session caching is enabled on a socket.
The other TLS_SESSION_CACHE_PURGE option allows to clear all of the
cache entries, releasing the memory allocated for sessions.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
In order to be consistent with what is possible in Devicetree, always
take a period in nanoseconds. Other scales or units may be specified by
using, e.g., the PWM_MSEC() macros (all of them converting down to
nanoseconds). This change then deletes the "_nsec" and "_usec" versions
of the pwm_set call.
Note that this change limits the period to UINT32_MAX nanoseconds,
~4.3s. PWM is, in generali, used with periods below the second so it
should not be a problem.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Similar to other APIs, this patch introduces the pwm_dt_spec structure
and associated helpers, e.g. PWM_DT_SPEC_GET() or pwm_set_cycles_dt().
The pwm_dt_spec reduces the boilerplate code needed when using
Devicetree. For example, if we have:
led: led {
...
pwms = <&pwm0 1 PWM_POLARITY_NORMAL>;
...
};
One can do now in the application:
struct pwm_dt_spec led = PWM_DT_SPEC_GET(DT_NODELABEL(led));
pwm_set_usec_dt(&led, LED_PERIOD_USEC, LED_PULSE_USEC);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In a first place, the PWM API operates on "channels", not "pins". While
the API calls could have been changed by _channel, this patch takes the
approach of just dropping _pin. The main reason is that all API calls
operate by definition on a channel basis, so it is a bit redundant to
make this part of the name. Because the `_dt` variants of the calls are
going to be introduced soon, the change to `_channels` + `_dt` would
make API function names quite long.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
All PWM API functions take a "pwm" parameter that indicates the selected
PWM channel. The variable name (pwm) and its documentation "PWM pin" is
misleading. This patch changes it to "channel" in line with the
terminology used in Devicetree (see DT_PWMS_CHANNEL... family of
macros).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Set TP in exception context so that it gets loaded into the CPU when
first running the thread. Set TP for secondary cores to related idle TLS
area.
Signed-off-by: Keith Packard <keithp@keithp.com>
When a stack overflow is caught by an MPU region, the stack pointer will
end up inside that area when the exception is handled. Handling the
exception involves pushing an exception frame onto the same stack. If
there's not enough space remaining below the faulting SP value, the
memory region below the stack will get corrupted.
We protect against this by making the stack guard larger than the 0x20
bytes necessary to hold an exception frame. To avoid lots of conditional
complexity here, the guard is set to 0x40 bytes if the MPU minimum size
is not larger than 0x20 bytes.
Signed-off-by: Keith Packard <keithp@keithp.com>
Making context switch cache-coherent in SMP is hard. The
KERNEL_COHERENCE handling was conservatively invalidating the stack
region of a thread that was being switched in. This was because it
might have (1) run on this CPU in the past, but (2) run most recently
on a different CPU. In that case we might have stale data still in
our local dcache!
But this has performance impact in the (very common!) case of a thread
being switched out briefly and then back in (e.g. k_sleep() for a
small duration). It will come back having lost all of its cached
stack context, and will have to fetch all that information back from
shared SRAM!
Treat this by tracking a "last_cpu" for each thread in the arch part
of the thread struct. If we're coming back to the same CPU we left,
we know we can skip the invalidate.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a pair of dt macros for specifying the pwm frequency in hertz or
kilohertz: PWM_HZ and PWM_KHZ. This is then converted in period
nanoseconds so it works as expected with the other definitions.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Update the new API to use K_USER as the flags for both
CONFIG_USERSPACE and CONFIG_TEST_USERSPACE. Also, fix the linker
script to properly include the suites, tests, and rules.
Fixes#44108
Signed-off-by: Yuval Peress <peress@google.com>
This splits common-rom.ld into smaller snippets so that these
chunks can be placed at different locations if so desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add all information from the ISO established events
and provide the information in the get_info function.
The use cases of each field heavily depends on what
the ISO streams are used for.
Most, if not all, of the field can be used by the
higher layers to improve quality and/or reliability
of e.g. audio streams that use ISO.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Fix alignment fo the cbprintf package withing the log message.
Aligning tests to pass.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Since the CAN header file is included directly by application code,
an application developer including this file and only applying
-Wextra to the application source files will see many warnings.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
Fix STM32 clock dt-bindings location as they were added during
the shift of bt-bindings location from include to include/zephyr.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Since gpio_dt_spec is finally available within spi_cs_control
struct, mark the old fields deprecated in order to use
gpio_dt_spec struct.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Co-authored-by: Jordan Yates <jordan.yates@data61.csiro.au>
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Co-authored-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
There is errata clarification (Errata ID:18700)
about subscriptions on fixed group addresses.
It is possible to subscribe models on non primary elements
on any fixed group address except all nodes address.
Devices should be able to receive messages on fixed addresses
even if they do not support the feature
to which the fixed group address belongs.
Signed-off-by: Aleksandr Khromykh <Aleksandr.Khromykh@nordicsemi.no>
STM32H7 series offer alias addresses to access some registers that could
be accessed by the M4 core on dual core variants.
For instance RCC_AHB3ENR could be accessed at following offsets:
- 0x0D4: Accessible from both cores
- 0x134: Accessible from C1 (M7) core
- 0x194: Accessible from C2 (M4) core (if any)
For most single core H7 variants, the two first addresses were accessible,
but for some others (stm32h7ax/stm32h7bx), only the 'C1 accessible'
was available.
This fact used to be hidden by the use of LL API to access these registers,
providing the required abstraction (an mainly using the first alias
when possible to simplify implementation).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add new scheme clock bindings for 'common' series:
- stm32f1_clock.h > compatible with f0/f1/f3 series
- stm32f4_clock.h > compatible with f2/f4/f7 series
- stm32l0_clock.h > compatible with l0 series
- stm32l1_clock.h > compatible with l1 series
- stm32l4_clock.h > compatible with g4/l4/l5/wb series
- stm32wl_clock.h > compatible with wl series
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Simplify and clean up driver code using STM32 clocks DT based macros.
Added STM32_FLASH_PRESCALER macro for this purpose.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Introduce a new scheme to define clock bingings on u5.
In a next steps, this new scheme will allow to provide u5 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On some series (H7, U5), it is possible define clock configuration
with disabled PLL outputs.
In that case, it is legit that matching pll property is not available.
Define corresponding STM32_PLLX_Y_DIVISOR macros using DT_PROP_OR
to avoid build issues in case prop is not available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Set bus binding values using registers offset values.
As a consequence update driver to take this into account
in clock_on and clock_off functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This new binding allows to work on providing stm32h7 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add an API that utilizes the ARM semihosting mechanism to interact with
the host system when a device is being emulated or run under a debugger.
RISCV is implemented in terms of the ARM implementation, and therefore
the ARM definitions cross enough architectures to be defined 'common'.
Functionality is exposed as a separate API instead of syscall
implementations (`_lseek`, `_open`, etc) due to various quirks with
the ARM mechanisms that means function arguments are not standard.
For more information see:
https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
impl
When threads are in more than one state at a time, k_thread_state_str()
returns a string that lists each of its states delimited by a '+'.
This in turn necessitates a change to the API that includes both a
pointer to the buffer to use for the string and the size of the buffer.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
