This add regulator driver for Smartbond DA1469X SOC.
Driver can control VDD, V14, V18, V18P, V30 rails,
full voltage range supported by SOC is covered.
For VDD, V14, V18, V18P DCDC can be configured.
Special VDD_CLAMP (always on) and VDD_SLEPP are added
to allow configuration of VDD in sleep modes.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Only RTC can be used as the idle timer for cortex-m systick. Set the
chosen node as RTC by default.
The idle timer will be enabled only if PM management is set.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Rather than configuring in serial_wakeup sample, define LPUART1 wakeup
line in wl.dtsi file.
Additionally make few cosmetic changes to nucleo_wl55rj overlay in
serial wakeup sample.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add soc power management for the STM32F4x chips.
One low power state is added supported by all chips from the family -
the Stop mode with voltage regulator in low-power mode.
The Stop mode for STM32F chips has to work with the IDLE timer -
CORTEX_M_SYSTICK_IDLE_TIMER, because PLL and HSI are disabled in the
Stop mode (Systick is not clocked). The only possible wakeup source is
RTC, which works as a IDLE timer for the Systick.
The exit latency may need to be adjusted per system, depending on the
system tick frequency and other variables.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
On STM32WL, the backup memory is defined as part of the TAMP peripheral.
This seems to be a deviation from the stm32 family where this memory is
defined as part of the RTC.
The STM32WL reference manual shows that tamp_pclk is connected to
rtc_pclk. This means that the clock required to run the TAMP peripheral
is the same as the RTC's. A quick port of BBRAM on STM32WL is achieved
by instanciating the bbram device as a child of the RTC and by modifying
the address offset to the first backup register from the rtc base
address.
Signed-off-by: Adrien Bruant <adrien.bruant@aalberts-hfc.com>
This commit moves configuration of hfxo from headers defined on board level
to device trees of SoCs.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
Add Verdin iMX8M Plus board with i.MX8MP SoC and ARM Cortex-M7 processor.
Add two targets (DDR and ITCM) for the iMX8M Plus board.
Port and documentation are based on NXP MIMX8MM EVK board.
This code is intented to be used with the Cortex-M7.
Signed-off-by: Gabriel Freitas <gabriel.freitas@toradex.com>
Add support for UART1 usage by adding uart1 node and configuration
to the i.MX 8ML devicetree include.
Signed-off-by: Gabriel Freitas <gabriel.freitas@toradex.com>
Add Renesas rzt2m gpio driver with basic functionality.
It supports pin mode configuration and writing/reading to/from gpio ports.
Includes dts changes to build blinky sample.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
This adds a new driver for Renesas RZ/T2M.
The driver allows configuration of pin direction,
pull up/down resistors, drive strength and slew rate,
and selection of function for a pin.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This adds a UART driver for the Renesas RZ/T2M
Serial Communication Interface.
The driver implements:
* Polling API,
* Interrupt-driven API.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This adds a new SoC: SOC_RENESAS_RZT2M
and a new board: rzt2m_startek_kit
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Co-authored-by: Roman Dobrodii <rdobrodii@antmicro.com>
Enable NXP FlexRAM in DTS and SOC code.
Do not configure flexram at runtime if the code is in the RAM.
Fix RT1060 DT to be more accurate.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The M4F subsystem has a dedicated GPIO controller with 24 available
pins. Add the node definition for the recently added driver.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Initialize the MDIO peripheral clock (normally done during GMAC
initialization) before trying any MDIO transfers, preventing startup
errors.
Signed-off-by: Nick Kraus <nick@nckraus.com>
Support NXP MRT on LPC55XXX SOC series, enable on
lpcxpresso55s69_cpu0, add test overlay to counter basic api test
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This device lost the reg property since 88c9d1fbaf, causing the
nucleo_l011k4 board to not build anymore. Add it back, 512 bytes should
be the right number for this chip.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Added initial version of Infineon CAT1 SDHC/SDIO driver
Added initial version of binding file for Infineon CAT1 SDHC/SDIO
driver
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
The variants of this family have different sizes of eeprom. This moves
eeprom definition from common family definition to device specific.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible
Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adding initial support for Renesas RA UART.
To avoid complicating initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA GPIO.
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA clock generation circuit.
It returns a fixed value to simplify the first commit to get the UART
working now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
The header file defines macros that are not used in the boards dts but on
the SoC level. They should be include where they are used.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
for nucleo_stm32g0b1 board.
the HSI48 clock is the clock used by default for the USB controller,
however its default tolerance is not enough for the USB specification,
leading to some random errors depending on many factors, including the
upstream HUB or host.
this commit adds an option in the device tree to enable the STM32 Clock
recovery system (CRS) using USB SOF packet reception as a reference,
which brings the HSI48 within the required accuracy for USB transfers.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Refactor the pinctrl nodes slightly so that the port devices are not
child of the main pinctrl node. This is because the pinctrl node is
being used as parent for pinctrl setting nodes itself, and having the
port nodes as child end up creating a circular depdency with the edt
child enumeration patch.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This files has been changed as part of a refactoring in 13a87081b9.
Unfortunately the refactoring introduced few issues:
- usage of devicetree macros before their definition
- usage of pinctrl label before the definition of the corresponding node
- removal of few node overrides that are causing build errors
Unfortunately there's no board usptream using this specific dts file, so
the issue has not been caught in CI and was only found downstream.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit adds the RTC device to the following
atmel sam devicetrees:
- sam3x.dtsi
- sam4e.dtsi
- sam4s.dtsi
- same70.dtsi
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
