This device driver supports ISSI is25w/lx032/64 series flash.
Only extended SPI mode(1s-1s-1s, 1s-8s-8s, 1s-1s-8s) is implemented.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
This patch adds a missing include directive to `spi.dtsi` in the
`build_all` configuration.The include is required because commit
2ac316465f introduced the use of `GPIO_ACTIVE_HIGH` and `GPIO_ACTIVE_LOW`
macros.
Signed-off-by: Patryk Koscik <pkoscik@antmicro.com>
When running the tests/drivers/memc/ram on the
adi_eval_adin1110ebz target, do not involve sram1, sram2
That will avoid warning about orphan section for
`DT_N_S_memory_10000000_P_zephyr_memory_region_STRING_TOKEN
and DT_N_S_memory_20040000_P_zephyr_memory_region_STRING_TOKEN
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Update CONFIG_SPI_IDEAL_TRANSFER_DURATION_SCALING
value for testcase to pass for higher transfer speeds.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Enable/disable devices as necessary to ensure memc test will test the
attached HyperRAM and no other memory nodes.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Currently, the `display_read_write` test execution can be suppressed
by `harness: display`, but since the display harness does not exist,
there is no way to run tests.
Using a fixture, it will be possible only to build if not specified,
and run tests if specified.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
- with the updates made to the spi_ll_stm32 driver,
we no longer need to configure the 16-bit frame/word size
in the DTS overlay file. The test_spi_word_size_16 testsuite
helps us verify the 16-bit frame mode supported on
the ST platform.
- remove testcases that use thoses files in testcase.yaml
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Place transfer buffers in non-cacheable memory when
CONFIG_NOCACHE_MEMORY=y. This change ensures that DMA transfer
buffers are allocated in non-cacheable memory on platforms where
CONFIG_NOCACHE_MEMORY is enabled. This avoids potential cache
coherence issues that are not handled by the SPI driver.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Set a convenient latency for each platform, since each platform
reacts differently to the driver.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The optee suite was failing in test_suspend() after a call to
k_aligned_alloc() which returns -ENOMEM. The alignment requirement is
4096 bytes, which seems reasonable, but what is odd about that is
that the alignment fails in spite of
CONFIG_SRAM_SIZE=145131134582784
and
CONFIG_HEAP_MEM_POOL_SIZE=270044
So there is plenty of memory available for this test and alignment
considerations should not be an issue.
Removing `CONFIG_DEBUG=y` solved the problem for me.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
add scenario in build-only operation to check for CI failures
when interrupt is disabled for the STM32 i2c driver.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
add arduino_i2c node in overlay files to be enable building the i2c_api
test on multiple stm32 boards,compatible for both i2c V1 and V2
driver.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
clock control is required for "fast instances" so assert clock
is enabled alongside PM DEVICE RUNTIME. Update UART tests to
reflect this requirenment.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
When testing y2k rollover, the seconds value can easily be off by one
since there is no guarantee that the RTC will be exactly on the second
boundary.
Relax the check to allow for a one second difference.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Ensure the alarm tests exercise rollover scenarios by setting RTC time
to a few seconds before midnight on a December 31st and alarm time to a
few seconds after midnight on the following day.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The nucleo_f746zg board doesn't handle RX/TX buffers in
non-cacheable memory when required. This leads to an error
in the test_adc_api with the log:
Supplied buffer is not in a non-cacheable region.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
If GPIO_DISCONNECTED is not supported by GPIO driver, then try to configure
the pin to be input, otherwise there will be some unstable signal between
two test pins.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The test which measures and validates transfer times is using the
helper spi_loopback_transceive() to perform the transfer. This
helper internally gets the spi controller, which is useful for
most tests, but for this one, it means the time to get and put
the spi controller is included in the transfer time measurement.
This commit gets the spi controller before calling
spi_loopback_transceive() which results in only the actual
transfer time being measured.
Before this commit, on the nrf54h20:
START - test_spi_complete_multiple_timed
Transfer took 745 us vs theoretical minimum 108 us
Latency measurement: 637 us
PASS - test_spi_complete_multiple_timed in 0.008 seconds
START - test_spi_complete_multiple_timed
Transfer took 700 us vs theoretical minimum 54 us
Latency measurement: 646 us
Assertion failed at ...
Very high latency
FAIL - test_spi_complete_multiple_timed in 0.027 seconds
After this commit:
START - test_spi_complete_multiple_timed
Transfer took 250 us vs theoretical minimum 108 us
Latency measurement: 142 us
PASS - test_spi_complete_multiple_timed in 0.008 seconds
START - test_spi_complete_multiple_timed
Transfer took 204 us vs theoretical minimum 54 us
Latency measurement: 150 us
PASS - test_spi_complete_multiple_timed in 0.008 seconds
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The spi_loopback test suite creates three internal threads. The
stack sizes for these threads is hardcoded to 512, which is to little
for some socs, namely the nrf54h20 cpuapp if pm device runtime is
enabled. Instead, determine the stack sizes the same way ztest
stack sizes are determined.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Currently, every boards that implement a memory controller add an entry
in tests/drivers/memc/ram/testcase.yaml. However, the configuration is
exactly the same for all the boards. So, we can just consider that any
board that declare "memc" capability has to be tested.
For the record here are the boards that has the memc capability:
adi/apard32690/apard32690_max32690_m4.yaml
adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml
adi/max32690evkit/max32690evkit_max32690_m4.yaml
arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml
arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml
arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml
atmel/sam/sam4s_xplained/sam4s_xplained.yaml
renesas/da1469x_dk_pro/da1469x_dk_pro.yaml
sifive/hifive_unmatched/hifive_unmatched_s7.yaml
sifive/hifive_unmatched/hifive_unmatched_u74.yaml
silabs/radio_boards/siwx917_rb4342a/siwx917_rb4342a.yaml
st/stm32f746g_disco/stm32f746g_disco.yaml
st/stm32f7508_dk/stm32f7508_dk.yaml
st/stm32f769i_disco/stm32f769i_disco.yaml
st/stm32h735g_disco/stm32h735g_disco.yaml
st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.yaml
st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml
st/stm32h750b_dk/stm32h750b_dk.yaml
st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.yaml
st/stm32h7b3i_dk/stm32h7b3i_dk.yaml
st/stm32h7s78_dk/stm32h7s78_dk.yaml
st/stm32n6570_dk/twister.yaml
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
set CONFIG_TIMESLICE_SIZE to 0 to disable time slicing.
Certain boards like nucleo_g071rb, nucleo_f091rc,
nucleo_l073rz will not start consecutive samplings as fast
as possible.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Test that the output of `adc_raw_to_microvolts_dt` matches the output of
`adc_raw_to_millivolts_dt` to the resolution of the latter.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add the `qemu_cortex_a53` configuration to run the build test
for the VIRTIO MMIO driver.
To add this test, we have split the virtio-pci and virtio-mmio test cases.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Introduce mock_i2c_error function in emulator in order to emulate i2c
errors for various registers
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
The STM32 Digital Camera Memory Interface Pixel Processor (DCMIPP)
is a multi-pipeline camera interface allowing to capture
and process frames from parallel or CSI interfaces depending on its
version.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Add `boards/qemu_x86_64.overlay` and some config modification
for testing `virtio,entropy` device.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit add support for the Omnivision OV9655 sensor,
a 1.3MPix Color SXGA (1280x1024 sensor).
Current driver only allow output of 320x240 and 160x120
resolution either in RGB565 or YUYV.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
