This device driver supports ISSI is25w/lx032/64 series flash.
Only extended SPI mode(1s-1s-1s, 1s-8s-8s, 1s-1s-8s) is implemented.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Most SPI NOR flash devices support a "fast read" command which uses
dummy bits between the address and the start of the data transfer. In
many cases, the maximum SPI clock speed of the device is lower for the
regular read command due to the limited time between the address and
data phases, so using the fast read command will remove this restriction
and allow for faster transfers.
Add a device tree flag to indicate that fast reads should be used for
the device.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Some Micron (and possibly other) SPI NOR devices implement a flag status
register which provides more information on the success/failure of erase
and program operations. In addition to better error checking, some of
these devices actually don't function properly if the flag status
register is not read after a program operation (subsequent reads will
only return 0xFF bytes).
Add a device tree parameter to indicate that the flag status register is
supported. When specified, the flag status register will be used for
ready/error checks rather than the standard status register.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add an erased-undefined property for Renesas RA series MCUS
data flash that will read back undefined values when erased
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
The tmp116 sensor driver also supports tmp117 and tmp119. Therefore rename
to indicate that is supports a range of tmp devices.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add a flash driver intended to handle various flash devices
connected over MSPI bus as long as they support JEDEC SFDP.
This is an initial commit providing only basic operations
in Octal I/O mode with some hard-coded values for Macronix
MX25Ux series chips.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support HyperFlash memory devices on a NXP S32 QSPI bus.
This driver uses a fixed LUT configuration that defined in HAL RTD
HyperFlash driver.
Driver allows to read, write and erase HyperFlash devices.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Create common source code to use for supporting HyperFlash.
Rename 'FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME' to
'FLASH_NXP_S32_QSPI_SFDP_RUNTIME' as a common kconfig.
Add the 'max-program-buffer-size' property to use for
setting memory pageSize, instead of using
'CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE' for setting.
Add the 'write-block-size' propertyto use for setting
the number of bytes used in write operations, it also
uses to instead of the 'memory-alignment' property.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
some flashes support special opcodes
for 4-byte addressing, that can be used
without switching to 4-byte mode.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add a driver for the MB85RSM1T FRAM chip.
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This concerns both `nordic,owned-memory` and `nordic,owned-partitions`.
Introduce a property named `nordic,access`, which is meant to replace
the `owner-id` and `perm-*` properties. It allows for describing how
multiple domains should access a single memory region, possibly with
different permissions per owner, but without having to create more than
one DT node for this purpose.
This change is also motivated by updated memory protection requirements
on the nRF54H20, which mandate that a given memory region must only be
reserved by one domain, even if multiple domains can have access to it.
This restriction is now described in the binding itself.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Currently flash controller driver builds and runs only on M7.
This patch supports enablement of the driver on M4 CPUs. The
main issue in using the driver on M4 is that LL_GetFlashSize()
to read the flash size works only on M7 as the internal register
is not accessible from M4. So to use the driver on M4, add a dt
property, bank2-flash-size, to configure flash size of bank2.
this will allow gradual support of flash controller driver
on M4 of all supported STMH7 boards by defining the above
dt property and testing it. Currently this is verified only
on STM32H747i-disco board.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
The ATXP032 is a NOR flash device that supports up to ~100MHz
octal SDR/DDR with 4MB nonvolatile memory.
The device driver uses MSPI bus API and could be used across different
SoC controllers that implement the MSPI bus API.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
The APS6404L psram is a quad SDR SPI device that runs up to 100MHz.
It can provide 8MB of external RAM for SoCs that supports XIP feature.
The device driver uses MSPI bus API and could be used across
different controllers that implement the MSPI bus API.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Improve the binding descriptions for the atmel,at24 and atmel,at25 EEPROM
compatibles. These compatibles work for a number of different EEPROM
families manufactured by vendors other than Atmel.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add a parameter to allow the configuration of the number of address
bytes used by the I2C master. This allows the driver to expose larger
buffer sizes.
Tested with standard linux at24 driver.
Signed-off-by: Bram Vlerick <bram.vlerick@openpixelsystems.org>
Add driver for IS66WVQ8M4 PSRAM, using the MCUX FlexSPI interface to
write data to the PSRAM device.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add new devicetree bindings for F4 and L1 series for configuration of
block size used in flash write operations.
Allow byte-size write operations in `flash_stm32f1x.c`. This file is
being shared between F0, F1, F3, L0 and L1 series. L0 and L1 series
allows for single byte writes.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
Add a set of bindings that will be used in the nRF54H20 SoC definition.
Extend the existing GPIOTE binding with properties needed for this SoC.
Also do a tiny clean-up in the bindings added recently for nRF54L15
(HFXO and LFXO).
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit updates the driver to use the flash layout pages,
rewriting it to utilize the flash_page_layout.c driver to
avoid duplicate code.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
This commit adds layput page cells to the atmel sam flash
controller and the flash node. These allow for describing
the actual flash page layout of each soc, allowing the
flash driver to fully utilize the capabilities of the
flash.
With this update, we unlock the following capabilties:
- utilize 2048 erase block size for small sectors
- utilize 16384 erase block size for large sectors
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
In the CONFIG_SPI_NOR_SFDP_MINIMAL configuration this value is hard
coded to 256 bytes. Make it configurable via devicetree.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Allow use of multiple mb85rc frams at contiguous i2c addresses as a single
big fram module.
Tested on mb85rc1mt used as two 32K modules, where the first one was at
mb85rc1mt's first i2c address and the second one at mb85rc1mt's second i2c
address.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Add support for flash NOR memory devices on a NXP S32 QSPI bus. The
driver uses a fixed LUT configuration assuming a default standard page
size and erase types, and allows to select between multiple read/program
instructions/modes. It is also possible to read the flash device
characteristics from the device at run-time as long as the memory is
JESD216 compatible, providing more flexibility.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Most available AT45 flash chips have their first two sectors shorter
than the consecutive ones. Usually, the first sector is marked as 0a
and has its size equal to eight pages (one block) and the second one
(usually 0b) is the complement to the size of a regular sector.
This commits modifies the driver so that erasing of these first two
sectors is performed correctly. This modified behavior is configurable
with a new DT property so that it is still possible to also use legacy
AT45 chips that do not feature such sector split. Such legacy chips
usually also do not support the chip erase and sector erase commands,
so two more DT properties are introduced to cover that.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Create and use a new `zephyr,i2c-target-eeprom` compatible
within I2C eeprom target driver that allows to use
that driver along with real atmel at24 EEPROM simultaneously.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
The documentation for the fixed-partitions binding is missing critical
information and is vague in other important respects. This is an
important binding that deserves to be crystal clear. Fix it.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Introduce driver for APS6408L PSRAM, built on top of the MCUX memc
driver for flexSPI. This driver supports operating the PSRAM in high
speed mode (200MHz or more). Note that in order to support this
PSRAM's alignment requirements, either ahb-read-addr-opt or
ahb-prefetch must be set for the FlexSPI instance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rename flexspi-hyperram driver to flexspi-s27ks0641, and update
function names. This driver is only capable of supporting the
s27ks0641 HyperRAM chip, as the lookup table given in this driver
is specific to the s27ks0641.
Rename the flexspi-hyperram binding to reflect this, to
prevent confusion from users.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix all line-length errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(line-length)'
Using a limit is set to 100 columns, not touching the commandlines in
GitHub workflows (at least for now).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
DTS property attributes are (by default) not required.
Explicitly specifying `required: false` is redundant.
Perhaps a warning to that effect would be useful.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
Add property mxicy,mx25r-power-mode to jedec,spi-nor binding for
controlling low power/high performance mode on Macronix MX25R* Ultra Low
Power flash devices.
- "low-power" configures the flash in ultra low power mode.
- "high-performance" configures the flash in high performance mode.
Signed-off-by: Gregers Gram Rygg <gregers.gram.rygg@nordicsemi.no>
