When not using dynamic interrupt mapping, various interrupt tables are
configured to be stored in read-only memory in the linker script.. Mark
them const so that the linker doesn't complain.
This affects _sw_isr_table, _irq_vector_table, and z_shared_sw_isr_table in
arch/common along with _VectorTable in arch/arc.
Signed-off-by: Keith Packard <keithp@keithp.com>
The difference between __irq_disable() and irq_lock() is that the former
essentially translates to `cpsid i`, whereas `irq_lock()` translates to
setting BASEPRI (on cores with BASEPRI). This means that using
irq_lock() does not disable zero-latency interrupts (ZLIs), which
reduces the potential execution latency of ZLIs.
In both isr_wrapper and _arch_isr_direct_pm() (which is just
really an implementation of ISR_DIRECT_PM()), we were using
__irq_disable() to disable all interrups, including ZLIs. But the code
executed with interrupts disabled handles waking up from idle, and so
must only be protected against regular interrupts being executed, not
ZLIs, which should have no effect on the correct execution of the code.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Introduce a Kconfig choice to select Pointer Authentication and Branch
Target Identification (PACBTI) features on Armv8.1-M Mainline CPUs.
The available options map to supported `-mbranch-protection` levels
(`standard`, `pac-ret`, `bti`, and combinations) documented at
https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html
These options enable hardware-assisted control-flow integrity mechanisms on
targets like Cortex-M85, and require a toolchain with PACBTI support, such
as GCC 14.2 or newer.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The original 'arch_pm_s2ram_resume' implementation saved lr on the stack
using 'push {lr}' and restored it using 'pop {lr}'. However, the Thumb-1
'pop' does not support lr as a target register, so this code would not
compile for ARMv6-M or ARMv8-M Baseline. r0 was added to these push/pop
later in 2590c48d40.
In 474d4c3249, arch_pm_s2ram* functions were
modified to no longer use the stack, which incidentally "fixed" this issue.
b4fb5d38eb reverted this commit and brought
back 'pop {r0, lr}' as-is, without taking compatibility into account.
Modify the sequence to use "pop {r0, pc}" which is supported on all
ARM M-profile implementations (v6/v7/v8 Baseline/v8 Mainline), and
add comments to (hopefully) prevent this issue from re-appearing.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add Kconfig option to dump only a portion of stack from the
current stack pointer to the stack end. This is enough to
let gdb reconstruct the stack trace and can significantly
reduce the dump size. This is crucial if the core dump needs
to be sent over radio.
Additionally, add another option to set the limit for the
dumped stack portion.
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
Move and rephrase the comment to better explain reason why obtained
IRQ number is decremented.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Allow to place the vector table section in SRAM with
CONFIG_SRAM_VECTOR_TABLE option for all cortex-m architecture that
have VTOR register.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Allow relocate_vector_table() to be overwritten. This is necessary if
the IRQ vector table is handled proprietary, e.g. before the zephyr
kernel is initialized. In this case we want this function to be empty to
avoid overriding the previous configuration.
Co-authored-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Signed-off-by: Eivind Jølsgard <eivind.jolsgard@nordicsemi.no>
The TOOLCHAIN_DISABLE_WARNING/TOOLCHAIN_ENABLE_WARNING macros are easier
to read and compiler agnostic.
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
IAR doesn't support the __volatile__ keyword, and since the
toolchain.h isn't included by these arm-specific files and
other arm-specific files already uses volatile, I've made
them all use volatile.
Signed-off-by: Lars-Ove Karlsson <lars-ove.karlsson@iar.com>
Add calls to sys_trace_idle_exit when leaving idle state. It is
used to track CPU load.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Multi-level interrupts should be handled in irq init. Only level1
interrupts going directly to interrupt controller need to be
initialized.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
What is the change?
- This reverts commit 474d4c3249
Why do we need this change?
- This commit was added because Cortex-M didn't have a valid
stack to make required functionality work however,
the previous commit fixes this and makes interrupt stack
available for use. This removes Arm specific limitation from
these generic APIs so revert the commit to reflect the same.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
What is the change?
- APIs `pm_s2ram_mark_set` and `pm_s2ram_mark_check_and_clear`,
used to set/check pm_s2ram magic marker,
no longer have Arm specific limitations.
Why is this needed?
- These APIs are generic and should not have arch specific dependency.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
One nmemonic was missed by f84342828cd1
That commit said:
The ARM Thumb-1 instruction set, used by ARMv6-M and ARMv8-M Baseline
cores, does not have a valid encoding for "immediate-to-register move
without affecting flags" instruction (i.e. `mov reg, imm`), and the only
valid variant of immediate-to-register move instruction for it is `movs`,
which affects the flags.
Since none of the register initialisation instructions used here are
flag-sensitive in their context, this commit changes `mov` to `movs`.
This fixes the compilation errors with Clang/LLVM, which is more picky
about the `mov` mnemonic usage and prints out an "invalid instruction"
error when `mov reg, imm` is specified in Thumb-1 mode.
Note that GNU assembler implicitly converts `mov reg, imm` to `movs reg,
imm` when assembling in Thumb-1 mode.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
Some basic flags that were hardcoded needed
to be moved to properties to be able to implement
alternative toolchains.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
This commit updates cortex_m related code to align it with the rules from
.clang-format. This is done to simplify future changes in these files as
we are about to implement use_switch support.
Some rules conflict with checkpatch and therefore some small part of the
code locally disable clang-format.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Encoding T3 allows for an offset of up to 12bits in size allowing for a
single instruction instead of 3.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Regular label are exported in the object file and cause gdb to consider
them as function start. Local labels on the other hand are not exported.
For example, using `disassemble z_arm_pendsv` after this change will
disassemble the whole function rather than stop at the first branch.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This reverts commit 42036cdbca.
Architecture specific code should not do preemption checking before context
switch. This is already handled by the scheduler, so duplicating it would
be redundant and error prone. These checks used to be necessary, but the
scheduler has been rewritten since then and the checks were removed in
3a0cb2d35d (kernel: Remove legacy preemption checking, 2018-05-23).
The check this reverts was also incorrect, as it didn't take scheduler
locking nor meta-IRQs into account.
Fixes#80574
Signed-off-by: Kalle Kietäväinen <kalle.kietavainen@silabs.com>
What is the change?
- Fixes#83660 allowing device to now enter suspend mode even if
CONFIG_DEBUG_THREAD_INFO is enabled.
Why is this needed?
- z_sys_post_kernel was cleared as part of #d778d5c
to "allow debuggers to display the correct thread state after
the first 3 instructions have run".
This is not required while resuming from suspend and
it prevents the device from entering suspend so,
move it out of resume path.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Define the generic _current directly and get rid of the generic
arch_current_get().
The SMP default implementation is now known as z_smp_current_get().
It is no longer inlined which saves significant binary size (about 10%
for some random test case I checked).
Introduce z_current_thread_set() and use it in place of
arch_current_thread_set() for updating the current thread pointer
given this is not necessarily an architecture specific operation.
The architecture specific optimization, when enabled, should only care
about its own things and not have to also update the generic
_current_cpu->current copy.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Mostly a revert of commit b1def7145f ("arch: deprecate `_current`").
This commit was part of PR #80716 whose initial purpose was about providing
an architecture specific optimization for _current. The actual deprecation
was sneaked in later on without proper discussion.
The Zephyr core always used _current before and that was fine. It is quite
prevalent as well and the alternative is proving rather verbose.
Furthermore, as a concept, the "current thread" is not something that is
necessarily architecture specific. Therefore the primary abstraction
should not carry the arch_ prefix.
Hence this revert.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The return value of the system_off call is overwritten by the the call to
pm_s2ram_mark_check_and_clear. As arch_pm_s2ram_suspend needs to specify
why system_off failed, we need to make sure the rv of system_off is moved
to a safe register before calling pm_s2ram_mark_check_and_clear and moved
to r0 als rv of arch_pm_s2ram_suspend when the suspend call exits.
Signed-off-by: Hessel van der Molen <hvandermolen@dexels.com>
The ARM Thumb-1 instruction set, used by ARMv6-M and ARMv8-M Baseline
cores, does not have a valid encoding for "immediate-to-register move
without affecting flags" instruction (i.e. `mov reg, imm`), and the only
valid variant of immediate-to-register move instruction for it is `movs`,
which affects the flags.
Since none of the register initialisation instructions used here are
flag-sensitive in their context, this commit changes `mov` to `movs`.
This fixes the compilation errors with Clang/LLVM, which is more picky
about the `mov` mnemonic usage and prints out an "invalid instruction"
error when `mov reg, imm` is specified in Thumb-1 mode.
Note that GNU assembler implicitly converts `mov reg, imm` to `movs reg,
imm` when assembling in Thumb-1 mode.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Moves the arch_swap() declaration out of kernel_arch_interface.h
and into the various architectures' kernel_arch_func.h. This
permits the arch_swap() to be inlined on ARM, but extern'd on
the other architectures that still implement arch_swap().
Inlining this function on ARM has shown at least a +5% performance
boost according to the thread_metric benchmark on the disco_l475_iot1
board.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
In some Cortex-M3 implementations SCB_VTOR bit[29] is called
the TBLBASE bit.
This enables setting VTOR to an SRAM address for qemu_cortex_m3
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Following the binding rename to "nxp,sysmpu", update the Kconfig
option to align with the binding name and to better reflect the
option's purpose.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
`_current` is now functionally equals to `arch_curr_thread()`, remove
its usage in-tree and deprecate it instead of removing it outright,
as it has been with us since forever.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
What is changed?
Use CMSIS SystemCoreClock via a dedicated flag instead of using
soc flags.
Why do we need this change?
This change is part of cleaning soc specific code out of arch folder.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Extend the ARM M-profile suspend-to-RAM implementation to be compatible
with all versions of the M-profile supported by Zephyr: ARMv6-M, ARMv7-M,
and ARMv8-M Baseline.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Wrap the CPU register save/restore operations (GPR and special registers)
in macros to make core logic simpler to follow. This is also a preparatory
step to introduce ARMv6-M and ARMv7-M support.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Use macros to wrap the interaction between the assembly code and the
struct __cpu_context. This helps making the assembly more readable.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Remove all xPSR-related registers from struct __cpu_context, and the
associated save/restore code in S2RAM code, as they are not needed:
* EPSR and IPSR are read-only - they cannot be "restored"
* Bits N, V, Z, C, V, Q, and GE (if DSP Extension is implemented) of APSR
could be restored, but this is not needed as the AAPCS indicates these
bits to be "undefined on entry to or return from a public interface"
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Gdb is typically able to reconstruct the first two frames of the
failing stack using the "pc" and "lr" registers. After that, (if
the frame pointer is omitted) it appears to need the stack pointer
(sp register) to point to the top of the stack before a fatal
error occurred.
The ARM Cortex-M processors push registers r0-r3, r12, LR,
{possibly FPU registers}, PC, SPSR onto the stack before entering the
exception handler. We adjust the stack pointer back to the point
before these registers were pushed for preservation in the dump.
During k_oops/k_panic, the sp wasn't stored in the core dump at all.
Apply similar logic to store it when failures occur in that path.
Signed-off-by: Mark Holden <mholden@meta.com>
This change was in the same commit previously reverted and seem to be
unrelated and should not be reverted.
Fixes the problem:
..... /swap_helper.S:432:(.text.z_arm_svc+0x26):
relocation truncated to fit: R_ARM_THM_JUMP11 against symbol
`z_arm_int_exit' defined in .text._HandlerModeExit section in
....core/cortex_m/libarch__arm__core__cortex_m.a(exc_exit.c.obj)
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add "memory" to the clobber list"
From GCC 14 the compiler optimizes away memory accesses that do not
impact the asm block. Adding the memory to the clobber list lets the
compiler know that the memory state is to be preserved.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Move the _main argument to the input list rather than the output one on
the asm block and change the spec to "r". The ASM block does not return,
so it does not make sense for it to expect any output.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Added casts to uint32_t in arch_timing_cycles_get() to handle the
wrap-around of the 32-bit cycle counter correctly.
Signed-off-by: Simon Tomschik <simon.tomschik@askgroup.global>
The S2RAM procedure requires marker checking after reset.
Such checking is performed on very early stage of the system initialization
and must ensure that the stack is not used due to the TLS pointer which is
not initialized yet.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
This reverts commit ec7943bb18.
This commit introduced a regression.
Let's revert it so we do not block development in main.
For more information see:
https://github.com/zephyrproject-rtos/zephyr/issues/79594
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Gdb is typically able to reconstruct the first two frames of the
failing stack using the "pc" and "lr" registers. After that, (if
the frame pointer is omitted) it appears to need the stack pointer
(sp register) to point to the top of the stack before a fatal
error occurred.
The ARM Cortex-M processors push registers r0-r3, r12, LR,
{possibly FPU registers}, PC, SPSR onto the stack before entering the
exception handler. We adjust the stack pointer back to the point
before these registers were pushed for preservation in the dump.
During k_oops/k_panic, the sp wasn't stored in the core dump at all.
Apply similar logic to store it when failures occur in that path.
Signed-off-by: Mark Holden <mholden@meta.com>
Add a new call for initializing cache on architectures that need that.
Avoid using SYS_INIT for this and instead call the hook in a fixed place
and run if implemented.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.
Replace z_arm_platform_init() with platform_reset().
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
