In the continuation of the previous commit, replace _OPT_ by _DOMAIN_
in macros relating to this feature.
hen, adapt drivers and tests to this new wording.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a bunch of missing "zephyr/" prefixes to #include statements in
various test and test framework files.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
In tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices
test suite, core_init.overlay configure msis to use pll-mode.
Since pll-mode is not configured for msik in spi1_msik variant the test
fails since both clocks should support the same configuration regarding
pll mode (an assert in raised in the driver).
Fix this in spi1_msik test variant.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that clock control drivers are enabled based on devicetree we
can remove any cases of them getting enabled by *defconfig and
proj.conf files.
Signed-off-by: Kumar Gala <galak@kernel.org>
Instead of enabling WOVCRO clock based on the SOC, use a configuration
to indicate support, so that each platform can specify if WOVCRO is
supported or not.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Intel ADSP CAVS is now a proper series with all CAVS SoCs running under
it. This will give us to Intel ADSP series:
- CAVS
- ACE v1.x
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Move to pass 'struct device *' instead of a 'char *'. This lets us move
from device_get_binding to DEVICE_DT_GET.
Signed-off-by: Kumar Gala <galak@kernel.org>
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commit adds a test case that configures an alternative clock source
for an ADC peripheral.
In case no alt clock is available, only the gating clock is enabled
and disabled.
Unlike the i2c and lptim test, the actual gating clock frequency is
not checked, because for the adc there seems to be no uniform way
to retrieve the frequency via the hal.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
For the STM32G0, STM32G4, and STM32WL enable the adc node in one
configuration, and select the PLL_P output as its clock source.
PLL_P divider is chosen to be 20 to make sure it's a unique frequency.
- g0, and g4 have pll as sysclk
- wl has hse as sysclock
The test configurations and the overlay-files are renamed accordingly.
All overlays that don't specify an alternative clock source still
make sure that the adc node is "okay" to be able to perform basic test.
The basic test only turns on and off the gate clock without checking the
frequency.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The test checks if the peripheral gating clock was correctly disabled
after the test, but accidentally the I2C_CLK was checked instead of the
LPTIM_CLK.
This commit fixes this by using __HAL_RCC_LPTIM1_IS_CLK_ENABLED instead.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The nucleo_wl55jc according to the datasheet does have a
NT2016SF-32M-END5875A 32MHz TCXO as HSE, therefore needs
enable the "hse-tcxo;" property to work, this was not the case
for the clock_configuration/stm32_common_devices test cases.
Additionally, remove the comment about about ST-Link clock,
because the source is the tcxo and not the ST-Link.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
STM32_DT_CLOCKS was designed to take a device tree node label name as
argument: STM32_DT_CLOCKS(uart1)
Change its implementation to take a node identifier instead:
STM32_DT_CLOCKS(DT_NODELABEL(uart1)).
This make its usage more flexible since the argument can now be extracted
from other DT macros such as DT_PARENT. Then, the following can be done:
STM32_DT_CLOCKS(DT_PARENT(child_node_label)).
Since it is now possible implement STM32_DT_INST_CLOCKS using
STM32_DT_CLOCKS.
Finally, update existing STM32_DT_CLOCKS users and convert
STM32_INST_CLOCK_INFO users to STM32_CLOCK_INFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Simple driver that allows one to choose the clock speed of xtensa cores.
It's basically a shim layer on top of SOC level driver.
Also, a really simple test case was added, mainly to ensure things are
build and are sane.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Since implementation of clock source selection in consumer device drivers
could be achieved without usage of a clock-names property and no
example of usage is provided up to now, remove this property from existing
examples.
Additionally, make it clear in stm32 clock control binding that it is
driver's responsibility to correctly access clock source information
and use it as required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a test section to enable device clock source selection testing.
Test targets I2C1 device which supports clock source selection
on all SOCs using this driver except L1
Initial test done on wb target.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move stm32_common tests to stm32_common_core before adding new folder
for device source selection tests.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
PLL input should be between 4 and 16MHz, so when MSI is set to 4MHz
fix PLLM can't be higher than 1.
Fix PLL1-NQR in consequence.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a stm32u5_devices test which aims at testing devices
clock control configuration on stm32u5 targets
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Make use of STM32_DT_CLOCKS_ macros to have the test work conditionally
based on alt clock presence.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add 2 clocks tests around device clock configuration on stm32h7.
For now, 'spi1_pllq_2_d1ppre_4' test variant is failed, which
illustrates issue reported in #41650.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to bring consistency in-tree, migrate all tests to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Rework test_*_freq to test HCLK freq instead of SYSCLK one, as it is not
correct to compare CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC with SYSCLK.
Additionally, add a test to verify use of AHB prescaler.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of testing SysClockFreq setting, we should instead check HCLK
setting which is the real zephyr CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
counterpart (core clock freq) and takes AHB prescaler setting into
account.
Additionally, update one test configuration to explicitly verify AHB
prescaler is correctly taken into account by clock driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove L0 and L1 targets from "sysclksrc_msi_48" test case as this
MSI range 11 is not an allowed value on these series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Test doesn't do any check on prescalers. Remove references and
existing user: wx_clear_clocks overlay.
Proceed to new factorization when possible.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Since they don't have impact on sysclock src configuration,
remove LSI/E clocks from clear clocks overlays.
This enables the possibility to factorize wl and wb clear clocks overlays
and brings some use cases factorizations as well.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Revise test cases naming:
- Replace _<series>_ by a .<series>. field in test cases naming
- Rename clear_clocks_msi.overlay to clear_msi.overlay
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fix selection of boards used:
- Remove superfluous/redundant configs
- Adapt to boards available on ST test bench
- fix typos
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To be functional, harness_config require a `harness: ztest` property,
add it.
Additionally, provide a comment to explain motivation behind this fixture.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Before introducing a new test for peripheral clocks,
rename existing stm32h7 test section by stm32h7_core.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
target is stm32fxx with clearing clock config
target is stm32fxx with pll from hsi clock config
target is stm32fxx with pll from hse clock config (with bypass)
target is stm32fxx with hse, hsi, clock config (no pll)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
target is stm32l4x/l5x with clearing clock config
target is stm32l4x/l5x with pll 64MHz from hsi clock config
target is stm32l4x/l5x with pll 48MHz from msi clock config
target is stm32l4x/l5x with pll 64MHz from hse clock config (with bypass)
target is stm32l4x/l5x with hse, hsi, msi clock config (no pll)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Testing the HSE on the nucleo_stm32g071rb requires a hw fixture
on the hw board : MCO signal must given by the STLink to the mcu.
Put a hardware fixture to activate the hse clock with by-passed
only if the SB17 is closed on the HW.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
target is stm32wb55 with clearing clock config
target is stm32wb55 with pll 48MHz from hsi clock config
target is stm32wb55 with pll 48MHz from msi clock config
target is stm32wb55 with pll 64Hz from hse clock config
target is stm32wb55 with hse, msi, hsi clock config (no pll)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
target is stm32wl55 with clearing clock config
target is stm32wl55 with pll 48MHz from hsi clock config
target is stm32wl55 with pll 48MHz from hse clock config
target is stm32wl55 with hse clock config (no pll)
target is stm32wl55 with msi clock config (no pll)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
