Make all series consistent with regard to where code is located and put
the power init code in power.c alongside other power related code.
Reduce soc.c per series to an empty file that can be removed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
initializing the SoC is the same across series, so put everything in one
place in the common code base.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
During transition into D3 state, watchdog timer have to be paused. FW can
resume it when core is re-enabled.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This PR adds a KConfig option that allows moving
all .noinit content related to wifi a net stack into external
ram. This free dram space to application.
Linker script files are also modified so that the content
are mapped into external ram.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Put ace headers alongside other headers. The contents of ace_v1x-regs.h
will be moved around to new headers being added across all series and
SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of enabling WOVCRO clock based on the SOC, use a configuration
to indicate support, so that each platform can specify if WOVCRO is
supported or not.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
If test for WOVCRO clock fails, code shouldn't just choose WOVCRO clock
as the lowest frequency one, but LPRO instead.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
For intel adsp platforms we have a common multiprocessing.c file and
then another multiprocessing.c for ace and multiprocessing_cavs.c for
cavs. Rename the cavs specific implementation to follow the convention.
There is not need to "cavs" suffix since the file is already inside its
specific directory.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Inside the common directory there were files that are CAVS specific and
are not used by ACE_V1X. Lets create a subdir called cavs inside the
common to put files that are common for only cavs plaftorms.
Note that there are still remaining code that in the common folder that
are using cavs namespace like "cavs_ipc_*" that may need some additional
work.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Intel ADSP CAVS is now a proper series with all CAVS SoCs running under
it. This will give us to Intel ADSP series:
- CAVS
- ACE v1.x
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to coredump dump the ram memory, it is necessary that we define
in the linker scripts two variable to indicate the start and the end of
the ram area. Adding these variables to ace linker script.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In order to coredump dump the ram memory, it is necessary that we define
in the linker scripts two variable to indicate the start and the end of
the ram area. Adding these variables to cavs linker script.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
cavs/version.h was never used by Zephyr, it was supposed to be needed by
SoF. This no longer seems to be the case, just removing it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Declare clock control in the shim header per SoC and remove ifdeffry
from the driver simplifiying it and making it ready for the next
platform.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Declare those register in the adsp_shim header instead of the code
applying ifdefs that limit the scope to only specific SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move those defines and values back to headers. Kconfig is not a good
place for this, later this should move to DTS.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
using once single header to support multiple socs and product
generations is error prone and not easily maintained.
Over time we have been adding conditional code in headers and extending
structs to support new HW features which becomes a problem.
Goal is to keep platform headers in sync with hardware specification and
allow of introduction of new platforms and hardware features by just
introducing a new SoC with its own set of headers.
This is now just a copy of existing cavs-shim.h with slight changes,
goal is to clean this up long term and sync with hardware datasheets and
align on naming as well.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move headers into the include/ folder per soc and rename fw_defs.h to
adsp_memory to align with SOF.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Uses a macro with a define flag to enable register dumps on the DSP
side. On the python side a simple booling flag.
The default disabled both debug flags and makes the tests
considerably quieter.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
Some tests was built failed due to cannot find the __imr macro:
Try to fix it by including the linker/section.h in soc.h.
Fixes#47830.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Those belong where other attribute macros are usually defined. They are
not xtensa or ADSP specific and are used across Intel SoCs on all
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of ifdeffing on SOCs and missing things along the way, maintain
platform definitions that are different among SoCs in one single file
per SoC and use data from that file critical spots.
In this case, we were checking for CAVS25, setting one value where
everything else was set to 0, so new SoC like ACE was getting 0 as well,
although it has the same value as TGL.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
