Now that counter drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Have the kscan device enabled in devicetree will now get the driver
enabled by default when CONFIG_KSCAN=y is set. So we can remove
driver enabling Kconfig values in various Kconfig.defconfig files.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that ADC drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the ADC.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that I2C drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the I2C.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that clock control drivers are enabled based on devicetree we
need to remove any cases of them getting enabled by Kconfig.defconfig*
files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a sensor and not
respect the devicetree state of the clock control. Additionally we
can get problems with prj.conf/defconfig getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that PWM drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the PWM.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that SPI drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the SPI.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that serial drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the serial.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that gpio drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the GPIO.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
Added mchp mec zephyr image generator python script. It takes
zephyr.bin as input and produces zephyr.mchp.bin.
The default behavior is to not pad to SPI flash size.
(Enable through CONFIG_MCHP_MEC_UNSIGNED_HEADER=y and
CONFIG_MCHP_MEC_HEADER_FLASH_SIZE_256K=y)
zephyr.mchp.bin is composed of:
1. First 4KB contains TAG at offset 0 and header at offset 0x100
2. Offset 0x1000 is the start of zephyr.bin which has been padded
to a multiple of 128 bytes.
3. Boot-ROM EC Info Block (128 bytes)
4. Boot-ROM Co-Signature Block (96 bytes)
5. Boot-ROM trailer (160 bytes) contains the SHA-384 digest of 2-4.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Linker files were not migrated with the new <zephyr/...> prefix. Note
that the conversion has been scripted, refer to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Correct eSPI flash macro so it not always results in zero,
leading to eSPI flash read operation in all cases:
Read, write, erase.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:
sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove a redundant symbol that was used as a proxy to enable CONFIG_PM.
If an application needs to enable PM, it should just enable PM subsystem
Kconfig options. Furthermore, there's no clue "SOC_POWER_MANAGEMENT" is
a Microchip specific option.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Aligning with the rest of PM API, replace pm_power_state_exit_post_ops
with pm_state_exit_post_ops.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The help for MCHP_ECIA_XEC is defined in
drivers/interrupt_controller/Kconfig.xec. defconfig files must not
re-define prompts or help, just modify the default value.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Fix for issue #41012 to allow compiler to treat
IRQn_Type to be more than 8-bit. This will ensure NVIC numbers
more than 127 (required for MEC172x device) will work
correctly with irq_enable() API
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Updates to MEC172x eSPI driver to support ACPI shared
memory region and EC Host Command Subsystem through
ACPI_EC1 and Embedded Memory Interface (EMI).
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
MEC172x eSPI driver, eSPI pin programming, interrupt updates related
to eSPI and other updates for MEC172x eSPI driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Uses the stats subsys to provide simple but useful debugging stats for
power management state changes and timing.
Removes the no longer needed PM_DEBUG config option
Replaces the use of PM_DEBUG for a test clock output pin for mec1501 and
adds in its place an SoC Kconfig option to enable it.
Adds a STATS_SET macro for assigning a value to a stat group field
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Microchip MEC172x series I2C driver implementing controller
and target modes. The driver implemenents its own I2C port
pin control functions and does not depended upon pinmux. Future
updates will make use of PINCTRL when that subystem is finalized.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add ADC driver version 2 for MEC172x using new in-tree headers
and device tree properties. Update the ADC shell for the new driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Microchip XEC has been using the standard NS16550 driver.
Using the standard NS16550 driver requires extra HW programming
for XEC UART in board level and did not support XEC GIRQ interrupt
programming. We add an XEC specific driver and remove UART specific
register programming from the board level and implement interrupt
support. Also, by implementing a SoC specific driver we can add
driver PM in the future.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Update the Microchip XEC pinmux driver to use system I/O
routine for read/write of registers instead of direct use
of volatile and CMSIS defines. Add GPIO port number to
bindings instead of using hard coded value from chip headers.
Modify SoC DTSI pinmux syntax, requires "pinmux: pinumx {..."
or the DT macros will not work. Since pinmux is used by MEC152x
we update its chip pinmux DT.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Create version 2 of the MEC GPIO driver to support MEC172x to not
interfere with MEC152x. When the MEC172x ECIA interrupt aggregator
driver is ready, this driver will use ECIA for registering GPIO
interrupt callbacks instead of maintaining its own interrupt table.
Add V2 DT binding.
Add the Kconfig configuration settings for the MEC172x GPIO
V2 driver at the SoC and board level.
Add port id to DT allowing use of DT FOR EACH macro in the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Define SoC hooks as weak symbols so this way applications can
overwritten them defining strong symbols.
The problem is that currently SoCs are defining these interfaces as
strong symbol inhibiting the possibility of applications bring their
own implementation.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
