Enable Zephyr device runtime power management mechanisms in Intel SSP
driver. This allows Zephyr to track usage reference for power
domain gating.
Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
This configuration does not work on some variants (simulator), reduce
the number to something that work on all variants.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of enabling WOVCRO clock based on the SOC, use a configuration
to indicate support, so that each platform can specify if WOVCRO is
supported or not.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Fixes configured DMA direction for HDA link in/out drivers.
Adjusts the number of channels for link in/link out to safe value
that seems to work on all tested parts.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
- adds properties 'group', 'index' and 'prescaler'.
- updates board's dts to include those properties.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This seems to cause a crash when running tests/boards/intel_adsp/hda and
also causing issues downstream on SOF.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.
Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.
By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Both idle and suspend states were just being used to set the cpu
idle. That is not necessary, if the pm policy does not find a suitable
power state the kernel automatically calls k_cpu_idle().
This remove unnecessary code and the weirdness of having
min-residency-us set to 0 and other arbitrary values.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Meteorlake support as part of the Intel ADSP family.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
This commit moves the hardware configuration for ledc
peripheral to the device-tree instead of Kconfig.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Bindings for Intel HDA now require the buffer alignment property to be
set.
Sets the property to 128 bytes for the common Intel cAVS device tree as
was implied by the tests cases.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Current write block size does not guarantee proper
write operation, what might cause corrupted data.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The ALH is an intermediary device, which acts as a hub and provides an
abstracted support for numerous sound interfaces (e.g. SoundWire).
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
On Espressif SoCs, the pin controller is a virtual device.
Pin settings are actually controlled in a distributed way.
Therefore, that node does not belong to the SoC bus.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
cavs15 uses different base addresses for IP blocks than the rest
and thus needs its own configuration in device tree.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add a GPIO pass-thru map for accessing the full range (0 to 39) of ESP32
GPIO pins by their datasheet number.
GPIOs 0 to 31 are mapped to gpio0 while GPIOs 32 to 39 are mapped to
gpio1.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The pinctrl support made usage of the 'peripheral'
property no longer required.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Adds hda link in and out drivers. The link in and link
out channels of HDA have small differences
with the host channels. Updates the existing
cavs_hda drivers and code to account for these
differences.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds an initial driver for HDA streams on cAVS. A common code base is
provided for all HDA streams while the drivers are identified
differently as they have small behavior differences.
Uses dma_status to describe the positions for read/write. Uses dma_reload
to inform when to move the read/write positions. This closely follows
how HDA is being used in SoF
Simple test case is provided for both drivers.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The dma nodes in device tree were entirely copy pasted. Rather than
doing that lets create a common intel_cavs.dtsi each specialization
then includes. This dedups the lpgpdma entries.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Previous Kconfig designated designware dma but did not define
the ip block in device tree. This caused warning when building tests.
The warnings caused CI to fail.
Really though the devices do all depend on the gpdma derivative and not
the generic DesignWare driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This is a slightly higher level Zephyr device that manages the host
IPC device for applications. There's an interface to make synchronous
and asynchronous calls, to receive commands via (interrupt context)
callbacks and emit async "done" notifications after processing is
complete. It should work for pretty much any application
architecture.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a new board to support Intel Tiger Lake H PCH variant of cAVS2.5.
Move common Kconfig options for cavs25 to soc level. No need to
replicate these for every board.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Intel's adsp needs to set, at a minimum, a clocking bit before the driver
can initialize the designware dma controller. In many ways it is the
designware dmac IP but with additional registers and functionality added
on top of it. So the code structure here follows how the hardware
appears to be designed, layered on top of the designware driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Current uart driver implementation is incompleted regarding the
usage of DT_INST_FOREACH_STATUS_OKAY. If uart0 and uart2 are selected,
build breaks due to peripheral number ordering, which would be
0 and 1 in this case. This fix PR fix this by re-working the macros
and setting proper uart peripheral instances in DTSI, required for signal
routing configuration.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
By enabling SMP option plus the APPCPU, also
completes the SMP port by adding the esp32
specific arch_sched_ipi() function
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
