Commit Graph

72 Commits

Author SHA1 Message Date
Kumar Gala
bb7854d79d dts: bindings: microchip: Remove unused cell related bits
various microchip bindings set 'girq-cells' and 'pcr-cells'
sections in the bindings.  However the bindings where for the
client nodes and thus do not need to set these.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-09 12:29:41 +02:00
Gerard Marull-Paretas
44250fe3d3 soc: arch: synopsys: move timer0/1 IRQ information to DT
timer0/1 IRQ information was hardcoded in soc.h, however, Devicetree is
nowadays a better place to describe hardware. Note that I have followed
existing upstream Linux code to do these changes.

Ref.
- https://elixir.bootlin.com/linux/latest/source/arch/arc/boot/dts/
  hsdk.dts
- https://elixir.bootlin.com/linux/latest/source/Documentation/
  devicetree/bindings/timer/snps,arc-timer.txt

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-03 07:46:14 -04:00
Gerard Marull-Paretas
00f51eff4e dts: riscv: andes: define machine timer
Define machine timer in Devicetree.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Gerard Marull-Paretas
e5e8822658 dts: riscv: neorv32: define machine timer
Define machine timer in Devicetree.

Ref. https://stnolting.github.io/neorv32/#_machine_system_timer_mtime

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Gerard Marull-Paretas
0da2ebc7e2 dts: riscv: telink: add DT entry for machine timer
Define machine timer in Devicetree.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Gerard Marull-Paretas
af2f5753d8 dts: riscv: starfive: align clint description with Linux
The CLINT (Core Local Interruptor) description was not aligned with
Linux. For example, there's no "riscv,clint0", but "sifive,clint0". The
peripheral is not described as an interrupt-controller either.

Ref. https://elixir.bootlin.com/linux/v5.18.14/source/arch/riscv/boot/
dts/starfive/jh7100.dtsi#L106

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Gerard Marull-Paretas
6de9fcf315 soc: riscv: gd32vf103: use nuclei,systimer compatible
After some analysis I found out that there's no machine timer provided
by the "riscv" vendor. There are some specs for the mtime/mtimecmp
registers (this is why we can have a single driver), but the actual
register layout or implementations differ amongst vendors. GD32 uses the
Nuclei implementation, named "system timer" in their documentation. This
patch aligns with vendor specs.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Kumar Gala
62f19cc6b3 dts: bindings: timer: device labels are now optional
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-16 16:21:39 +00:00
Kumar Gala
4aae32640f dts: arm/arm64: remove DTS 'label' property requirement from gic and timer
The armv8 timer, arm gic, and arm gic-v3-its don't use or need the
devicetree label property.  Update the dts bindings to not require it and
remove setting of the label property in dts files.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-06-16 09:48:12 -05:00
Georgij Cernysiov
063e9447e0 dts: bindings: timer: stm32: lptim exclude countermode
LPTIMER has a different `countermode` meaning.
We shall exclude introduced property from lptim bindings.

Alternative property (e.g. `external-mode`) can be added
later on to support external counter mode.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-04-15 11:59:16 -07:00
Georgij Cernysiov
20dfae9cfd dts: bindings: timer: stm32: add countermode
Adds `countermode` property. That allows to
configure timer counter mode.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-04-15 11:59:16 -07:00
Gerson Fernando Budke
8427f5e9b1 drivers: timer: Add sam0 tc32 support to pinctrl
This add support to pinctrl at Atmel sam0 timer tc32 driver.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-03-24 15:45:37 -07:00
Gerson Fernando Budke
986388453f drivers: counter: Update sam driver to use pinctrl
This update Atmel sam counter driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-03-24 15:45:37 -07:00
Marius Scholtz
38d684f8f1 drivers: counter: sam: expose RC reg to DT
Exposes the RC register so that the initial value can be set in
the device tree. This is useful in the case where the timer
generates an event but an interrupt is not required.
e.g generate event to sample adc on RC register match.

Tested on Atmel SMART SAM E70 Xplained Ultra board

Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
2022-01-21 14:25:49 -05:00
Daniel Leung
44462723f5 timer: hpet: make legacy interrupt routing optional
On some platforms, HPET is not wired to trigger IRQ 2.
This would make HPET non-functional if the legacy
interrupt routing bit is set in the global config
register. This adds a DTS flag so the driver won't
set the bit to enable legacy interrupt.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-14 14:46:21 -05:00
TOKITA Hiroshi
306128799f dts: bindings: timer: Correct compatible name of riscv,machine-timer
dts/bindings/timer/riscv,machine-timer must have compatible name
riscv,machine-timer. nuclei,machine-timer is wrong, correct it.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-01-14 09:49:53 -06:00
Gerard Marull-Paretas
384f360989 dts: bindings: timer: add gd,gd32-timer
Add bindings for GigaDevice GD32 timers.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-07 14:58:27 -06:00
TOKITA Hiroshi
d79d4f0bea riscv_machine_timer: Enable to use divided clock for the machine timer
GD32V SoC uses divided clock from core-clock for machine timer clock.
Add config of clock divide factor to support GD32V.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
Alexandre Bourdiol
37175e8643 dts: bindings: stm32: move "st,prescaler" to timers instead of pwm
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
Also prescaler is common to all PWM channels of the same timer.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
For compatibility reason temporarily keep pwm binding to avoid
breaking boards out of tree.
Block st,prescaler property in lptim binding
as lptim doesn't use this property for now.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-11-16 09:55:30 -06:00
Jay Vasanth
c214c59548 Microchip: MEC172x: eSPI driver
MEC172x eSPI driver, eSPI pin programming, interrupt updates related
to eSPI and other updates for MEC172x eSPI driver.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2021-10-26 09:27:20 -04:00
Martí Bolívar
f259790bf8 dts: bindings: fix file names
Make sure binding file names match their compatibles.

Done with a script.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-10-20 07:33:04 -04:00
Felipe Neves
16be75b68f dts: added dts binding for esp32c3
interrupt controller, also places its relevant
peripheral sources allowing drivers to use the
DT macros instead of espressif headers.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-10-02 14:33:24 -04:00
Toby Firth
893bfc0fc1 drivers: counter: added ctimer driver for lpcexpresso55s69
Added shim driver for the CTIMERs for the lpcexpresso55s69 board.

Fixes: #22705

Signed-off-by: Toby Firth <tobyjfirth@gmail.com>
2021-08-24 17:13:22 -04:00
Scott Worley
7075b700b7 Microchip: MEC172x: Device tree constant property cleanup
Microchip XEC two custom DT properies girqs and pcrs cell sizes
are defined as constants. There is no need to replicate these
is the chip DTSI since the value cannot be changes. Fix the syntax
of the cell size constant to match the naming convention used
thoughout DT.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-08-09 13:06:01 -04:00
Scott Worley
dd1a9559be Microchip: XEC RTOS timer: Add MEC172x support to driver
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-27 09:29:34 -04:00
Piotr Mienkowski
1145986096 drivers: Add Atmel SAM counter (TC) Driver
Add basic counter driver based on Timer Counter (TC) module for Atmel
SAM family.

Remarks:
- The driver is not thread safe.
- The driver does not implement guard periods.
- The driver does not guarantee that short relative alarm will trigger
  the interrupt immediately and not after the full cycle / counter
  overflow.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2021-07-26 05:13:40 -04:00
Martí Bolívar
1f1beadeff dts: bindings: timer: fix up multi-line strings
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-06-14 21:49:57 -04:00
Julien Massot
860cfcbde4 dts: bindings: add binding for Renesas RCar CMT timer
Add device tree binding for Compare Match Timer that can
be found on various Renesas RCar SoC.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-04-22 10:38:45 +02:00
Sun Amar
cc43b9c648 gecko pwm: add bindings files
Add bindings files for the pwm and the timer for the
efr32 soc family

Signed-off-by: Sun Amar <sun681@gmail.com>
2021-04-02 18:45:33 -04:00
Piotr Mienkowski
d6f2ba8011 dts: add support for Atmel SAM Timer Counter (TC)
Add support for Timer Counter (TC) on SAM E70/V71 series.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2021-03-18 10:20:17 +01:00
Mulin Chao
e5caae8e0a driver: timer: npcx: add system kernel timer support.
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.

It includes:
 - A system timer based on an ITIM64 (Internal 64-bit timer) instance,
   clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
 - Its prescaler is set to 1 and provide the kernel cycles reading
   without handling overflow mechanism.
 - A event timer based on an ITIM32 (Internal 32-bit timer) instance,
   clocked by LCLK which frequency is 32KHz and still activated when ec
   entered "idle/deep idle" power state for better power consumption.
 - Its prescaler is set to 1 and provide timeout event mechansim.
 - Compensate system timer which clock is gating for better power
   consumption after ec left"idle/deep idle" power state.

This CL passed starve, timer_api, and timer_monotonic test suites.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-02-19 22:39:53 -05:00
Kumar Gala
3fff3852fa dts: Rename compatible arm,arm-timer to arm,armv8-timer
The compatible for the ARMv8 timer should have been arm,armv8-timer and
not arm,arm-timer.  The dts binding file name was correct, just the
compatible was wrong.  Rename dts, binding, and associated code to use
arm,armv8-timer.

Fixes #31946

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-04 07:04:28 -05:00
Hake Huang
38c53b6347 dts-binding: dts/bindings/timer: add gpt freq in dts binding
add gpt freq in dts binding

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2021-01-22 08:34:49 -06:00
Cheryl Su
f060540b33 dts: it8xxx2 device tree and binding
This commit is about it8xxx2 platform device tree.
Add driver's binding files, and one device tree as sample.

Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
2020-12-16 08:47:36 -05:00
Martin Åberg
bb5a565aaa timer: Add support for GRLIB GPTIMER
This adds support for GRLIB GPTIMER general purpose timer used in
LEON3/4/5 systems.

One of the GPTIMER subtimers is used to generate periodic interrutps
for announcing ticks. Another subtimer is used as upcounter for the
cycle_get_32() service.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-11-13 14:53:55 -08:00
Peter Bigot
ae6b236d26 dts: nordic: add CC count to RTC and TIMER nodes
The number of capture/compare registers available on a peripheral
should be exposed in devicetree.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-11-11 13:20:25 +01:00
Francois Ramu
7545b7888a dts: stm32: timer define a new DT binding for LPTIM
Adds a new LPTIM binding for stm32 soc,
based on the timer binding. This will makes a specific filter
on dt_compat_enabled("stm32,lptim")

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-05-29 14:13:05 +02:00
Kumar Gala
8eafcc32db drivers: counter: sam0_tc32: rework devicetree support
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks from devicetree.  Move the prescaler setting
from Kconfig to devicetree as well.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-25 13:33:56 -05:00
Kumar Gala
fe573b6e23 dts: atmel: sam0: Add clocks for ADC and TCn devices
Add clock references for ADC and TC devices.  Update the bindings for
these devices to require clocks property and update the dtsi files to
have the clock info.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-25 13:33:56 -05:00
Stephanos Ioannidis
dd75bccaca dts: bindings: Fix xlnx,ttcps binding compat
The `xlnx,ttcps` binding, despite having the file name of
`xlnx,ttcps.yaml`, had the compatible property of `cdns,ttc`.

While it is true that the Xilinx ZynqMP platform embeds the Cadence
Triple Timer Counter (TTC) IP core, its TTC differs from the original
Cadence core in that it implements 32-bit counters, instead of the
16-bit counters defined in the original; hence, the Xilinx variant is
not compatible with the original Cadence version and should be treated
as a different device.

This commit changes the `xlnx,ttcps.yaml` compatible property to
`xlnx,ttcps` for the above reasons.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-21 14:20:17 -04:00
Daniel Leung
dbe69d9031 dts: bindings: microchip,xec-rtos-timer: add GIRQ fields
Add the girq and girq-bit fields to the binding. This allows
encoding GIRQ related information inside device tree.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-03-11 21:16:16 -04:00
Carlo Caione
6f36300219 drivers: timer: Add per-core ARM architected timer
ARM cores may have a per-core architected timer, which provides per-cpu
timers, attached to a GIC to deliver its per-processor interrupts via
PPIs. This is the most common case supported by QEMU in the virt
platform.

This patch introduces support for this timer abstracting the way the
timer registers are actually accessed. This is needed because different
architectures (for example ARMv7-R vs ARMv8-A) use different registers
and even the same architecture (ARMv8-A) can actually use different
timers (ELx physical timers vs ELx virtual timers).

So we introduce the common driver here but the actual SoC / architecture
/ board must provide the three helpers (arm_arch_timer_set_compare(),
arm_arch_timer_toggle(), arm_arch_timer_count()) using an header file
imported through the arch/cpu.h header file.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2020-02-01 08:08:43 -05:00
Ulf Magnusson
2934ee2cda dts: bindings: Remove 'title:' and put all info. into 'description:'
Add any useful information from 'title:' to the 'description:' strings
(e.g. explanations of acronyms), and remove 'title:' as well as any
copy-pasted "this binding gives a ..." boilerplate.

Also clean some description strings up a bit.

Some other things could probably be cleaned up (replacing 'GPIO node'
with 'GPIO controller' on controllers for consistency, for example), but
I kept things close to the original to avoid accidentally messing up.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-12-18 11:52:45 +01:00
Francois Ramu
0ae7023405 driver: timer: st_stm32: add lptimer management to stm32xx series
This patch introduces the support of the LowPower Timer
 for the STM32xx from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-11-08 10:04:21 -06:00
Ulf Magnusson
b9240a3cbc dts: bindings: Preserve newlines in descriptions
With https://github.com/zephyrproject-rtos/zephyr/pull/20185, multi-line
descriptions will be formatted nicely, but using '>' breaks it, because
it removes internal newlines (including between paragraphs).

See https://yaml-multiline.info/.

Replace 'description: >' with 'description: |' to encourage '|'. That'll
prevent '>' from getting copied around and messing up long descriptions.

This will lead to some extra newlines in the output, but it's fine.
Line-wrapping messes up any manual formatting.

The replacement was done with

    $ git ls-files 'dts/bindings/*.yaml' | \
          xargs sed -i 's/description:\s*>/description: |/'

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-10-30 07:55:51 +01:00
Charles E. Youse
3038209695 drivers/timer/hpet.c: migrate to devicetree
This driver was still using CONFIG_* values to determine its address,
IRQ, etc. Add a binding for an "intel,hpet" device and migrate this
driver to devicetree.

Fixes: #18657

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-17 22:37:09 +08:00
Ulf Magnusson
6e46a64a48 dts: bindings: Shorten license headers
Shaves a bunch of lines.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-09-07 10:25:02 -05:00
Ulf Magnusson
a0fceff1a2 scripts: dts: Simplify and improve 'compatible' matching
Instead of

    properties:
        compatible:
            constraint: "foo"

, just have

    compatible: "foo"

at the top level of the binding.

For backwards compatibility, the old 'properties: compatible: ...' form
is still accepted for now, and is treated the same as a single-element
'compatible:'.

The old syntax was inspired by dt-schema (though it isn't
dt-schema-compatible), which is in turn a thin wrapper around
json-schema (the idea is to transform .dts files into YAML and then
verify them).

Maybe the idea was to gradually switch the syntax over to dt-schema and
then be able to use unmodified dt-schema bindings, but dt-schema is
really a different kind of tool (a completely standalone linter), and
works very differently from our stuff (see schemas/dt-core.yaml in the
dt-schema repo to get an idea of just how differently).

Better to keep it simple.

This commit also piggybacks some clarifications to the binding template
re. '#cells:'.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-09-07 10:25:02 -05:00
Kumar Gala
da9859533e dts/bindings: Convert bindings to new include syntax
Convert from:

inherits:
    !include spi-device.yaml

to:

include: spi-device.yaml

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-09-07 10:25:02 -05:00
Ulf Magnusson
fcd665a26c dts: bindings: Have 'required: true/false' instead of 'category: ...'
The 'category: required/optional' setting for properties is just a
yes/no thing. Using a boolean makes it clearer, so have
'required: true/false' instead.

Print a clear error when 'category:' is used:

    edtlib.EDTError: please put 'required: true' instead of 'category:
    required' in 'properties: foo: ...' in
    test-bindings/sub-node-parent.yaml - 'category' has been removed

The old scripts in scripts/dts/ ignore this setting, and only print a
warning if 'category: required' in an inherited binding is changed to
'category: optional'. Remove that code, since the new scripts already
have the same check.

The replacement was done with

    git ls-files 'dts/bindings/*.yaml' | xargs sed -i \
        -e 's/category:\s*required/required: true/' \
        -e 's/category:\s*optional/required: false/'

dts/binding-template.yaml is updated as well.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-09-07 10:25:02 -05:00