In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Refactors interrupt controller drivers to use the shared driver class
initialization priority configuration, CONFIG_INTC_INIT_PRIORITY, to
allow configuring interrupt controller drivers separately from other
devices. This is similar to other driver classes.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEFAULT to preserve
the existing default initialization priority for most drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Change to use macro DT_FOREACH_CHILD_STATUS_OKAY to avoid routing the
interrupts to the disabled cores.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
We only need to distribute interrupts to CPU Cores with the count
of CONFIG_MP_NUM_CPUS, and get Core's MPID from CPU nodes in dts.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The GIC interrupt controller driver is using a custom init function
called directly from the prep_c function. For consistency move that to
use SYS_INIT.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
It is desired to have the peripheral writes completed to clear the
interrupt condition and de-assert the interrupt request to GIC before
EOI write. Failing which spurious interrupt will occur.
A barrier is needed to ensure peripheral register write transfers are
complete before EOI is done.
GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point
of view. However these writes may pass over different interconnects,
bridges, buffers leaving some rare chances for the actual write to
complete out of order.
GICv3 ICC EOI system register writes have no ordering against nGnR(n)E
memory writes as they are over different interfaces.
Hence a dsb can ensure from core no writes are issued before the
previous writes are *complete*.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Add basic driver for GIC V3 interrupt controller.
This implementation supports
- distributor, re-distributor and cpu interface initialization
- configuration and handling of SPI, PPI and SGI.
- V2 Legacy mode is not supported and uses system interface.
Current implementation supports GIC secure state only.
All interrupts are routed to Secure EL1 as 'irq' by configuring
them as Group1 Secure.
TODO:
- MPIDR based affinity routing setting.
- percpu redistributor probe
- message based SPI and SGI generation api
- EL1NS support. Legacy mode support.
- LPI/ITS is not supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Fixing ICFGRn register access with `sys_{read,write}32`
since this register is not byte-accessible.
Type of `val` changed to u32 to match reg width.
Fixes#24339
Supersedes #24422
Signed-off-by: Bartlomiej Flak <flakbartlomiej@gmail.com>
This commit fixes the field definition names for `GICD_ICFGR`, which
were incorrectly prefixed with `GICC_`.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The current Generic Interrupt Controller (GIC) driver makes use of the
multi-level interrupt mechanism and `irq_nextlevel` public interface.
This is a less-than-ideal implementation for the following reasons:
1. The GIC is often used as the main interrupt controller for the
Cortex-A and Cortex-R family SoCs and, in this case, it is not a 2nd
level interrupt controller; in fact, it is the root interrupt
controller and therefore should be treated as such.
2. The only reason for using `irq_nextlevel` here is to interface the
architecture implementation to the interrupt controller functions.
Since there is no nesting or multiple instances of an interrupt
controller involved, there is really no point in adding such an
abstraction.
3. 2nd level topology adds many unnecessary abstractions and results
in strange coding artefacts as well as performance penalty due to
additional branching.
This commit refactors the GIC driver interface as follows:
1. Remove the current GIC driver interface based on the multi-level
interrupt mechanism and the `irq_nextlevel` public interface.
2. Define the GIC driver interface in
`include/drivers/interrupt_controller/gic.h` and allow the arch
implementation to directly invoke this interface.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The current GIC driver implementation only supports the GIC-400, which
implements the GICv2 interface.
This commit refactors the GIC driver to support multiple GIC versions
and adds GICv1 interface support (GICv1 and GICv2 interfaces are very
similar).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
