Commit Graph

3 Commits

Author SHA1 Message Date
Neil Armstrong
a737999b5b interrupt_controller: gicv3: add Interrupt Translation Service support
This implements support for the optional Interrupt Translation Service
(ITS) module of the GICv3 Interrupt Controller.

The current implementation is designed for MSI/MSI-X interrupt delivery
in mind.
The gicv3 driver calls each ITS INVALL command when LPI interrupts are
enabled/disabled.
A simple atomic integer is used to allocate unique LPI INTIDs to ITS
users.
CPUs numbers are directly mapped as ICIDs into the Collections Table.

As a limitation it doesn't support indirect Device table to simplify
implementation but may use a large amount of memory.

INV, DISCARD, MOVI and MOVALL commands are not implemented.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-09-28 19:45:29 -04:00
Jaxson Han
36006ed1ba drivers: gicv3: GIC with single secure mode
The Cortex-R 64-bit processor only supports GIC with single
security mode

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-04-13 07:47:44 -04:00
Stephanos Ioannidis
11d0f0a294 drivers: interrupt_controller: Refactor GIC configurations
The current GIC configuration scheme is designed to support only one
specific type and version of GIC (i.e. GIC-400 that implements the
GICv2 interface).

This commit adds a set of GIC version configuration symbols that can
be selected by the SoC configuration to specify which version of GIC
interface is implemented in the SoC.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-12-19 11:05:27 -05:00