Commit Graph

953 Commits

Author SHA1 Message Date
Hake Huang
8add9219a7 drivers: timer : cortex_m_systick MAX_TICKS protection
when CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC set to 960M
and CONFIG_SYS_CLOCK_TICKS_PER_SEC set to 100
the MAX_TICKS will be zero or even negative value, which is not
expected.
so need add a protection here downgrading the accuracy to
its as high as possible

also add build message to show that tickless has no effect

fixes: #36766

there used to be a workaround, not a fix,
either change the CONFIG_SYS_CLOCK_TICKS_PER_SEC=200
or
CONFIG_PM to set the CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
to 32678

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2025-07-22 08:19:55 -04:00
Scott Worley
ef4ec43e63 drivers: timer: microchip: xec: Microchip MEC one kernel timer driver
We want to simplify the maintenance burden and confusion of having
more than one driver for the same kernel timer peripheral used on
all Microchip MEC parts. The XEC version of the driver was converted
register definitions in the driver. Register access is performed using
Zephyr sys_read/write architecture specific inline routines. Driver DT
YAML was updated to use phandle for the 32-bit basic timer used for
ARCH_HAS_CUSTOM_BUSY_WAIT support, basic timer max value property,
and GIRQ interrtup aggregator hardware information.
SoC part Kconfigs, chip level/board level DTSI updated to use the
unified driver.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2025-07-19 15:39:40 -04:00
Declan Snyder
efdd8580ca soc: nxp: Flatten MCX SOCs
Turn MCX series into families.

Reasoning:
 1. The MCX SOCs are quite different from each other and having them all
    under one family in the HWMv2 hierarchy is fruitless because there
    are so many differences that it is confusing to try to introduce
    family-level code and configs since they would each only apply to a
    subset of the series. There is almost nothing that can be shared
    between all of them. Which is why there are comments in the MCX
    family files saying not to put anything in them. This is a technical
    waste.
 2. Therefore, turning all of them into families is almost 0 effort and
    makes sense. It will allow these different types of MCX to be
    further subdivided into series in the future as the MCX portfolio
    expands and such division will be necessary as new SOCs within each
    letter family are released.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-07-19 13:25:29 -04:00
Erwan Gouriou
a884e3b537 drivers: timer: stm32 lptim: Fix the st,timeout runtime check
Existing check failed on correct settings.
Add an assert to fasten the debug.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2025-07-19 13:22:44 -04:00
Erwan Gouriou
e99db0ddd2 drivers: timer: stm32_lptim: Fix behavior of st,timeout
To be consistent with the definition of label stm32_lp_tick_source,
be sure "st,timeout" is taken from the LPTIM defined as lp_tick_source.

Then, fix the computation of lptim_time_base.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2025-07-19 13:22:44 -04:00
Peter Mitsis
ec80ab5bb6 drivers: timer: Clean up Cortex-M systick Kconfig
Makes the choice CORTEX_M_SYSTICK_LPM dependent upon the
CORTEX_M_SYSTICK to prevent its default from showing up in
the .config of projects that do not use the CORTEX_M_SYSTICK
timer driver.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-07-04 16:40:31 -10:00
Adam Kondraciuk
e77f942cff drivers: timer: nrf_grtc_timer: add last_count initialization
The GRTC counter is not cleared at startup, therefore the
`last_count` variable needs to be initialized accordingly.
This change:
- Prevents overflow of the `sys_clock_announce()` int32_t parameter
- Ensures the correct uptime value, which should be reset during
  initialization

Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
2025-06-30 15:23:44 -05:00
Mahesh Mahadevan
14b1ba15ac drivers: timer: Fix the logic to compensate the clock when turned off
The original logic relied on the tick passed in. This method
is inaccurate as the tick value passed in was the exit latency.
Update the code to calculate the remaining time left and set
a counter using this value.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2025-06-27 18:21:25 -05:00
Peter Wang
f8b14155f0 boards: frdm_mcxa166, frdm_mcxa276: add ostimer support
1. add the ostimer
2. by default, the systick is used.
3. The ostimer could be tested with below configure in xxx.overlay:
&systick {
    status = "disabled";
};

&ostimer0 {
    status = "okay";
};
And below configure in xxx.conf:
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000

Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
2025-06-27 08:54:06 -10:00
Mickael Bosch
888bde94be drivers: timer: handle the stm32u0 target
Configure the lptim to wake-up from sleep.

Signed-off-by: Mickael Bosch <mickael.bosch@linux.com>
2025-06-25 15:33:47 -10:00
Tomas Groth Christensen
089c4613ba driver: timer: enable 64 bit cycle counter for MCUX_OS_TIMER
Selects TIMER_HAS_64BIT_CYCLE_COUNTER as an dependency for MCUX_OS_TIMER
This already is supported in the timer implementation in
drivers/timer/mcux_os_timer.c

Signed-off-by: Tomas Groth Christensen <tgc@foss.dk>
2025-06-24 20:03:01 -10:00
Alessandro Manganaro
6244e9307e drivers: timer: Fix interrupt management in stm32 lptim timer
Fix interrupt management issue in stm32 lptim timer

Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
2025-06-23 13:44:15 +02:00
Alessandro Manganaro
e5ded3d71a drivers: timer: Fix conversion issue in stm32 lptim timer
Using correct macro to convert stdby time in LPTIM counter

Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
2025-06-23 13:44:15 +02:00
Peter van der Perk
32d68bed22 drivers: timer: remove fsl_power.h for MCXN series
Initial it was only removed for mcxn236 but mcnx947 would fail to
compile then

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
2025-06-20 13:26:41 -04:00
Krzysztof Chruściński
6717a37421 drivers: timer: nrf_rtc_timer: Optimize z_nrf_rtc_timer_get_ticks
Converting absolute system ticks to RTC ticks is simple. It needs to be
multiplied by CYC_PER_TICK (which by default is 1). Complex algorithm
was used when driver was not tracking current 64 bit tick and function
was returning uint32_t.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-06-12 09:26:29 -07:00
Adam Kondraciuk
a280fbf9fb drivers: timer: nrf_grtc_timer: Add frequency parameter for K32SRC
Add frequency value for LFCLK sources to be used when `lfxo` node
is not present.

Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
2025-06-12 11:32:59 +02:00
Tim Lin
97cdedec80 drivers/timer: it51xxx: Compensate time calculation to reduce drift
The EC timer runs at 9.2 MHz, which leads to a non-integer number of
ticks per microsecond. This causes slight overestimation when delays
are computed using whole ticks (e.g., using 10 ticks for 1 µs).
To address this, the busy wait calculation is adjusted with a
compensation factor to minimize cumulative timing error over time.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-06-06 08:45:43 +02:00
Ruibin Chang
ec6b34d870 drivers/timer/it51xxx: remove not used timer
Timer 7 is not used in timer driver, which means that timer
driver doesn't initialize timer 7, it's just declared in dtsi.
So I remove it, timer 7 will be used as alarm timer for counter driver.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2025-06-05 12:33:29 +02:00
Andrew Davis
2edb6d2517 drivers: timer: ti_dmtimer: Do not require systick_timer node label
This driver currently only supports one instance of this timer and uses
it as the system clock. The instance is selected by being the first one
listed in DT in all places except sys_clock_driver_init() where it uses
the node label "systick_timer".

This driver should be fixed to correctly support multiple instances
of this timer, and the one used for the system timer should be selected
based on a flag or alias, not based on label.

For now simply use the 0th instance like everywhere else which removes
the need to have this node labeled a special way and makes no functional
changes to current users.

Signed-off-by: Andrew Davis <afd@ti.com>
2025-06-03 17:08:37 +02:00
Nhut Nguyen
a1874b11cc drivers: system timer: Initial support for RZ/G3S
Add System Timer driver support for Renesas RZ/G3S

Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
2025-06-03 17:08:30 +02:00
Sreeram Tatapudi
02f2beab29 drivers: timer: Add support for IFX Low power timer
Adding support for low power timer to enable low power modes

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2025-05-29 20:19:18 -04:00
Tony Han
d251ecd116 drivers: timer: sam: add pit64b timer for sama7g5
Use pit64b0 as systick, make "kernel sleep/uptime" commands work.

Signed-off-by: Tony Han <tony.han@microchip.com>
2025-05-28 08:14:08 +02:00
Chen Xingyu
42fb9067e4 drivers: timer: riscv_machine_timer: Use reg-names to access registers
This commit updates the riscv_machine_timer driver to resolve MTIME and
MTIMECMP register addresses by their `reg-names` instead of relying on
index order.

This improves clarity and robustness in DTS bindings, and is a prerequisite
for handling cases where not both MTIME and MTIMECMP registers are present
or accessible.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
2025-05-27 19:04:22 +02:00
Miguel Gazquez
be9549be60 soc: Add support for the WCH CH32V303
Adds support for building an image for the ch32v303.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
2025-05-24 18:03:53 +02:00
Miguel Gazquez
2b91c467f2 modules: Update hal_wch
Update hal_wch.

As the hal upstream changed name, there is now a name conflict.
Rename ch32fun.h to hal_ch32fun.h to fix this conflict.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
2025-05-24 18:03:53 +02:00
Lin Yu-Cheng
1e38f94473 drivers: timer : fix rtmr timer.
RTMR clear the interrupt status bit in the init and isr function.

Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
2025-05-22 02:21:12 +02:00
Anas Nashif
5fe84d5b69 arch: nios2: remove arch
Remove architecture and dependencies.
Remove altera HAL supporting nios2

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-05-15 20:01:05 -04:00
Camille BAUD
dd51655b25 drivers: add CH32V203 to wch systick
Adds CH32V203 to the systick timer driver

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-05-14 11:02:52 +01:00
Alberto Escolar Piedras
98b05b3062 drivers/timer/native_sim: Use upper case long suffix
For better readability

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2025-05-13 12:09:30 +02:00
Michael Hope
3dbf080698 hal: wch: widen the checks to include the CH32V family
Expand the current systick compatibility to include the CH32V00x
series. Change the HAL compatibility to include all of the CH32V
family.

Signed-off-by: Michael Hope <michaelh@juju.nz>
2025-05-09 01:40:22 +02:00
Duy Nguyen
ad42e4d87d driver: timer: Support for RX system timer
This commit add a system timer driver for Renesas RX using the
CMT peripheral. The driver supports both system ticks and
high-resolution cycle counting
- Configures CMT0 as the system tick timer
- Configures CMT1 as a free-running cycle timer for precise
  time tracking
- Handles timer overflows to maintain a continuous cycle count.
- Implements sys_clock_cycle_get_32() and sys_clock_cycle_get_64()
  for  high-resolution timing
- Supports Zephyr tickless kernel mode by tracking elapsed cycles
- Enables interrupt-based tick announcement using CMT0

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Yuichi Nakada <yuichi.nakada.sx@renesas.com>
2025-05-02 09:18:16 +02:00
Michael Hope
1d7a095779 soc: wch: move from qingke-v2 to the more specific qingke-v2a
The CH32V003 CPU is a QingKe V2A while others in the CH32V00x series
use the QingKe V2C. Prepare for adding support for the CH32V006 moving
to the more specifc qingke-v2a, moving some cases of SOC_CH32V003
actually meaning SOC_FAMILY_QINGKE_V2A.

Signed-off-by: Michael Hope <michaelh@juju.nz>
2025-04-26 10:55:45 +02:00
Hoang Nguyen
1462d3e972 drivers: timer: Add initial support for RZ/A2M
Add timer support for RZ/A2M

Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
2025-04-25 14:05:01 +02:00
Amneesh Singh
d7bb10d85c drivers: timer: ti_dmtimer: provide timer IRQ for tests
This patch allows ti_dmtimer to provide the symbol z_sys_timer_irq_for_test
whenever tests are enabled. Not providing this results in failing some
kernel test cases which require this symbol.

Signed-off-by: Amneesh Singh <a-singh7@ti.com>
2025-04-22 14:02:44 +02:00
Hao Luo
b9f05070be drivers: timer: Add support for Apollo510 SoC system timer (STIMER)
This commit adds support for Apollo510 SoC in ambiq stimer driver

Signed-off-by: Hao Luo <hluo@ambiq.com>
2025-04-21 20:04:31 +02:00
Titan Chen
5179463750 drivers: timer : fix rtmr and slow timer.
RTMR use slow timer be the busy_wait timers,
only ARCH_HAS_CUSTOM_BUSY_WAIT if slow timer disabled.

Signed-off-by: Titan Chen <titan.chen@realtek.com>
2025-04-21 12:42:28 +02:00
Hao Luo
6f4b92d64d soc: ambiq: Optimize the inclusion relationship of header files
Optimized the inclusion relationship of header files

Signed-off-by: Hao Luo <hluo@ambiq.com>
2025-04-17 09:06:18 +02:00
Tim Lin
a531e71376 drivers/timer: Add timer driver of it51xxx
Add timer driver for ITE it51xxx series.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-08 10:48:26 +02:00
Khanh Nguyen
7ae800a0c9 drivers: timer: Add ULPT timer for power management on Renesas RA MCUs
drivers:
- Added ULPT timer driver in `renesas_ra_ulpt_timer.c`.
- Updated `clock_control_renesas_ra_cgc.c` for ULPT clock settings.
- Updated `uart_renesas_ra8_sci_b.c` for power management support.
- Updated `CMakeLists.txt` and `Kconfig` to integrate ULPT timer.
- Added `Kconfig.renesas_ra_ulpt` for ULPT-specific configurations.

dts bindings:
- Added `renesas,ra-ulpt.yaml` for ULPT node bindings.
- Added `renesas,ra-ulpt-timer.yaml` for ULPT timer bindings.

modules:
- Updated `Kconfig.renesas_fsp` to support ULPT and LPM.

Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
2025-04-03 08:41:08 +02:00
S Mohamed Fiaz
701be0c331 driver: sleeptimer: siwx917: Add siwx91x Sleeptimer driver
This commit enables the Sleeptimer driver support for the siwx917 device.

Signed-off-by: S Mohamed Fiaz <fiaz.mohamed@silabs.com>
2025-04-03 06:24:54 +02:00
Raffael Rostagno
4b8dc5f3ff drivers: esp32: Update for shared intc
Drivers update to use shared interrupt allocator for Xtensa
and RISCV devices.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-04-02 19:02:27 +02:00
Adam Kondraciuk
042c5c6252 drivers: timer: nrf_grtc_timer: Move up GRTC clock selection
Selection of the LF clock source for the GRTC should be performed
as early as possible, before starting GRTC.

Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
2025-04-01 11:52:26 +02:00
Krzysztof Chruściński
40ab30f23f drivers: timer: nrf_grtc_timer: Optimize z_nrf_grtc_timer_get_ticks
Converting absolute system ticks to GRTC ticks is simple and algorithm
can be simplified. Legacy algorithm was copied from nrf_rtc_timer which
back then was working on 32 bits only.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-03-31 14:31:48 +02:00
Titan Chen
10f7218df4 drivers: timer: rts5912: Fix RTMR accurate issue.
Fix RTMR_ADJUST_LIMIT and RTMR_ADJUST_CYCLES

Signed-off-by: Titan Chen <titan.chen@realtek.com>
2025-03-28 21:51:08 +01:00
Anisetti Avinash Krishna
139211772c include: zephyr: sys: time_units: Make z_clock_hw_cycles_per_sec unsigned
Convert z_clock_hw_cycles_per_sec to unsigned int to increase
supported frequency range.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2025-03-28 12:21:07 +01:00
Lucas Tamborrino
c6f84d0ba2 boards: espressif: esp32c6: Add LP Core board support
Add ULP Coprocessor board support for C6.
This requires a change in the board qualifier depending on the build
target.
Update esp32c6 overlay and configuration files to the proper name.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2025-03-21 17:05:20 +01:00
Declan Snyder
b990f96feb dts: counter: Remove old kinetis lptmr binding
Remove deprecated nxp,kinetis-lptmr compatible string
which is superseded by nxp,lptmr compatible due to
removing family specific name.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-03-20 17:14:28 +01:00
Declan Snyder
f013e20bc5 soc: nxp: Add missing resolve of system timer cfg
These socs were missing a config line to disable SYSTICK if the LPTMR is
configured for the system timer, similar to how other SOCs do this for
alternative system timers than systick.

This fixes build errors in the case where that lptmr kconfig is enabled.

Also, the LPTMR kconfig should be default no because it is a secondary
option for the system timer, being lower resolution than systick. This
also resolves build errors.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-03-20 17:14:28 +01:00
Aksel Skauge Mellbye
7dc6fb442f drivers: timer: silabs: Fix calculation of next tick
In the case where more than a full tick was unannounced when
sys_clock_set_timeout() was called, the timer driver would
subtract it from the next timeout. However, this is already
done by the caller through the elapsed() function in timeout.c,
leading to the timer interrupt firing too early.

With this fix, SYS_CLOCK_TICKS_PER_SEC can be increased to the
full speed of the low frequency timer. The underlying sleeptimer
API must be called with a timeout of at least 1, and will if needed
increase the value to the minimum value required by the hardware.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2025-03-18 16:42:42 +01:00
Peter Mitsis
701aab92e2 kernel: Add Z_IS_TIMEOUT_RELATIVE() macro
Introduces the Z_IS_TIMEOUT_RELATIVE() macro to help ensure that
checking for relative/absolute timeouts is consistent. Using this
macro also helps ensure that we get the correct behavior when using
32-bit timeouts (CONFIG_TIMEOUT_64BIT=n).

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-03-17 02:21:02 +01:00