Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The NXP Pixel pipeline engine (PXP) is a 2D DMA engine capable of
accelerating display rotation, color space conversion, and limited
2D blending operations. This DMA driver only supports rotation of a
framebuffer, via a set of custom dma_slot values. Only DMA channel 0
is supported or utilized.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added a parameter inside the Channel Number macro since
the LPC55S36 expects an address rather than a static number.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
The Broadcom pcie setup has a devicetree dependency like:
/pcie/paxdma -> /pcie/pcie -> /soc/pl330
Add a separate init symbol for iproc_pax_v2 so that these gets
initialized in order, fixes this error:
$ west build -p -b bcm958402m2_m7 tests/kernel/common \
-DCONFIG_CHECK_INIT_PRIORITIES=y
...
ERROR: /pcie/paxdma@4e100800 POST_KERNEL 40 < \
/pcie/pcie@4e100000 POST_KERNEL 50
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix for bug:
https://github.com/zephyrproject-rtos/zephyr/issues/59802
The DMA controller only supports one transfer size, but
the Zephyr DMA driver api allows specifying a source_data_size
and dest_data_size which might be different. An old
version was always using dest_data_size for the transfer
size (variable is called "width"), but a recent change
made the driver use the MIN for the source and dest data
sizes. The MIN choice breaks the I2S driver because it
always set source_data_size to 1, but dest_data_size was
typically 4 for like two-channel 16-bit PCM data. So the
old driver worked using dest_data_size, but the new driver
broke I2S using MIN since source_data_size was 1.
To prevent confusion, change the DMA driver to assert that
source_data_size and dest_data_size are the same.
Also assert that the source_address and dest_address for
each block_config are properly aligned for the transfer size,
since that is a documentated requirement for the DMA controller.
Also rename max_xfer to max_xfer-bytes to be more clear what
the units are, and use this value in many places that
are comparing block_size in bytes rather than converting
block_size to words by dividing by width and
then comparing to NXP_LPC_DMA_MAX_XFER.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Fixes a bug in intel_adsp_gpdma_release_ownership(). Before fix, this
function actually did nothing for ACE platform and the ownership was
not released. Now ownership is released to host CPU + DSP.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Add a Kconfig to have the ability to fine tune the amount of RAM that
the driver uses based on the number of channels expected to be used.
Most of the code is already there but just need this Kconfig to get the
benefit of it by reducing the size of the statically created arrays.
Also change the number of channels field in the configuration to a byte
instead of a 32 bit integer because that should be sufficient to
describe the number of DMA channels.
Rename LPC DMA Driver Kconfigs with namespace to MCUX_LPC
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
remove the sdk based TOTAL_DMA_CHANNELS macro and instead just use the
zephyr driver's num_of_channels field
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The block data length field should be in bytes. Setting this to a value
that is not a multiple of the data size results in a user setting error.
Running the ADC DMA test prior to this commit:
west build -p -b nucleo_u575zi_q zephyr/tests/drivers/adc/adc_dma
E: Transfer Error.
I: tc: 0, ht: 0, dte: 0, ule: 0, use: 1
E: DMA sampling complete, but DMA reported error -5
Existing tests using DMA on the nucleo_u575zi_q were not effected
because they only use a data size of one and continue to function
as expected:
west build -p -b nucleo_u575zi_q zephyr/tests/drivers/spi/spi_loopback \
-DOVERLAY_CONFIG="overlay-stm32-spi-dma.conf"
SUITE PASS - 100.00% [spi_loopback]: pass = 1, fail = 0, ...
west build -p -b nucleo_u575zi_q zephyr/tests/drivers/dma/loop_transfer
SUITE PASS - 100.00% [dma_m2m_loop]: pass = 3, fail = 0, ...
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
The tables for the dest and src data width constants were incorrectly
swapped. This commit uses the correct constants and renames the tables.
This change is only cosmetic for the stm32u5 since these constants are
the same but the existing names were probably inherited from another
driver where the p_*/m_* prefix was more appropriate.
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
Enable DMA error interrupts so that transfer errors are logged and
reported to the callback.
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
A "switch" statement in intel_adsp_hda_dma_status() seems to be
missing a "break". The second "break" is unneeded but seems to be a
part of the coding style.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add specific init priority for the stm32 DMAMUX device higher
than the CONFIG_DMA_INIT_PRIORITY, to be sure that the DMAMUX
initialization always comes after the stm32 DMA device init.
Its default value is set to 41 when the DMA_INIT_PRIORITY is
KERNEL_INIT_PRIORITY_DEFAULT (=40).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Replace the otrig configuration semaphore with a spinlock.
This will allow the dma_config function to be called from an ISR
and it will no longer shift the burden of waiting to be able to configure
the dma otrigs to the caller of the function, since the driver
will just spin on the lock until it can configure them, instead of
returning an error.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This patch fixes following compilation error when compiling using clang
drivers/dma/dma_stm32.c:364:42: error: equality comparison with
extraneous parentheses [-Werror,-Wparentheses-equality]
if ((config->head_block->source_address == 0)) {
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~
drivers/dma/dma_stm32.c:364:42: note: remove extraneous parentheses
around the comparison to silence this warning
if ((config->head_block->source_address == 0)) {
~ ^ ~
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch ensures that the power domain to which the current HD DMA
instance belongs is power-up first.
In addition, it initializes the channels when coming out of SUSPEND
state, so this operation will be performed also when the stream is
started after the DSP comes out of D3 state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Fix the OTRIG related build error in the DMA LPC
by defaulting num_of_otrigs to 0 if a plarform using
the LPC DMA does not specify this property in devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Added to the configuration function to enable
channel chaining for the DMA_LPC that utilizes
the total of the SOC OTrig channels.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Driver should just say the channel is not busy if
it is not setup rather than returning an error.
Also, change the channel index to int8_t rather
than uint32_t since it is being assigned negative
values and that width is more appropriate.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Added intel LPSS DMA interface using dw common to support
usage of internal DMA in LPSS UART, SPI and I2C for
transfer and receive operations.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Added support for 64bit address source and destination
usage for dw common.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
1. Transfers are not limited by XFERCOUNT transfer length of
LPC DMA descriptor. Added code to handle block sizes
greater than XFERCOUNT.
2. Use the reload_en flag to decide if we should setup
a circular descriptor chain.
3. Improve handling of source and destination width.
4. Number of DMA descriptors are defined by a Kconfig value.
5. Changed the dma_reload function to handle transfers
greater than XFERCOUNT.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Change init level of the mcux lpc dma driver to be
PRE_KERNEL_1 because some other hardware drivers
used on the same platforms as the lpc dma will be
dependent on the LPC DMA and are also initialized
in PRE_KERNEL_1, such as the Flexcomm UART driver
when using UART_ASYNC_API.
Therefore, remove k_malloc from init function and
make those variables statically defined instead of
heap allocated.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Some miscellaneous fixes to LPC DMA driver regarding status tracking:
- If a DMA channel has not been configured for any transfer,
there will be a bug caused by the virtual channel being -1
and then trying to index -1 into the driver data structs.
Add -EACCES return code to indicate this situation.
- Return -EINVAL from get_status if channel number is invalid
- Update the busy flag in the LPC DMA callback function.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
According to the coding guidelines "dynamic allocation is not allowed".
This commit removes handling invalid DMA capable buffers by allocating
temporary buffer in a valid memory region, considering them as errors.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add GDMA support for esp32s3.
Remove suspend/resume since they are optional and do
the same as start/stop.
Fix possible null pointer derreference.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Make use of positive status values in the DMA callback to pass
info to the DMA client after a successful DMA operation.
A completed DMA transfer uses the status 0 while a reached
water mark uses the status 1.
Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
CAVS platforms are not fully integrated with zephyr. Some of the
registers are still programed from SOF side. This feature can be enabled
for those platforms later when integration is fully done.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Adding function that is allowing to release ownership of the DMA. When
DSP is no longer using dma instance it ownership can be released.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is refactoring device power flow routine. DMA instance will
not be power up after kernel initialization if device power management
is enabled. Power menager will power up device and its power domain if
device will be in use and disable it when it's no longer needed.
The DMA disabling part has not yet been implemented.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The address increment logic was looking at both source
and destination parameters together. Separate them so
we can set one.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
CFG register uses fields that are not defined in Synopsys databook of
Designware AHB DMA Controller.
Since current Zephyr code uses this driver only for the
intel_adsp_gpdma driver I assume that those fields are specific to
this DMA which is not the standard Designware one.
This patch allows to use either the standard Designware register or
the Intel one.
Signed-off-by: Sylvain Chouleur <schouleur@graimatterlabs.ai>
Add a second instance of DMA to the stm32 dma driver from the DTS
That can be found in the stm32H5 serie, where 2 GPDMA with 8 channels
are available. Rebuilding with Macro.
Use the dma_channels property of the dedive tree to count the nb
of dma channels: 16 or 8 (like in stm32h5).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".
Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
