Test that `pm_device_driver_init` puts devices into the appropriate
state depending on the devicetree configuration.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Update the expected power domain behaviour in the tests in line with
the driver implementation changes.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Startup power domains according to the expected final state given the
power supply and PM device runtime support.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Let the driver compile without `PM_DEVICE_POWER_DOMAIN`, in which case
the driver only controls the GPIO, without notifying dependant devices.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Adds a helper function for initializing devices into the expected power
state, through the devices `pm_device_action_cb_t`. This eliminates code
duplication between the init functions and the PM callback.
The expected device states in order of priority are:
* No power applied to device, `OFF`
* `zephyr,pm-device-runtime-auto` enabled, `SUSPEND`
* Otherwise, `ACTIVE`
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Implement `gpio_pin_get_config` for the stellaris platform, and by
extension `qemu_cortex_m3`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This is a follow-up to commit 4c20403629.
CONTAINER_OF() cannot be used to obtain the device pointer from its
data pointer as this data is not contained in the device structure.
Instead, use a dedicated member in the device data structure to store
the device pointer.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for flash NOR memory devices on a NXP S32 QSPI bus. The
driver uses a fixed LUT configuration assuming a default standard page
size and erase types, and allows to select between multiple read/program
instructions/modes. It is also possible to read the flash device
characteristics from the device at run-time as long as the memory is
JESD216 compatible, providing more flexibility.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The NXP S32 QSPI controller acts as an interface to up to two serial
flash memory devices, each with up to eight bidirectional data lines,
depending on the platform. It is based on a LUT enginee to interface
through commands with different memory types including flash NOR and
Hyperram.
This patch adds support for the QSPI in S32K344 which supports a single
memory device (side A) with up to four bidirectional data lines and SDR
only. Nevertheless, the memory controller is implemented flexible enough
to be extended to support more feature-rich QSPI blocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add Kconfig RISCV_SOC_HAS_CUSTOM_SYS_IO symbol so that a riscv
SoC can set to specify that it has a custom implementation for
sys_io functions.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This commit aligns TWIM shim to utilize memory-region property.
The memory-region is not required property that enables user
to specify placement of dma buffers in memory region.
It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
There are two different i2c node properites `zephyr,flash-buf-max-size`
and `zephyr,concat-buf-size`. In the end max value of that two is used
to define size of the message buffer.
It's redundant to store both values in device config structure.
Changed config structure to contain only bigger value.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Variant of JSON_OBJ_DESCR_ARRAY_ARRAY that can be used when the
structure and JSON field names differ.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Add initial version of Infineon CAT1 counter driver
Add initial version of binding file for Infineon
Add counters to psco6 dtsi
Add external trigger pin that runs counter
Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
Fix various incorrect maintainer file entry for directories. These
are currently matching files, but would break few scripts if we were to
upgrade the CI image to Python 3.11 due to a change in behavior of
Path.glob().
Fixes various:
MAINTAINERS.yml: glob pattern '...' in 'files' in area '...' does not
match any files
on machines running Python 3.11 or newer.
Link: https://docs.python.org/3/library/pathlib.html#pathlib.Path.glob
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The check currently only runs if the maintainers file itself is changed,
but that means that the check is going to miss every PR that moves
directory or delete files that can potentially trigger an error.
This check is cheap to run, just run it unconditionally.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The correct paths are soc/xtensa/espressif_esp32
and soc/riscv/espressif_esp32, not soc/xtensa/esp32
and soc/riscv/esp32.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
The intent of this change is to add custom shell configurations for
intel_socfpga_agilex* based boards. As of now, configurations are
added for 'intel_socfpga_agilex5_socdk' board.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Each PSCI interface versions have different DT compatible strings
like arm,psci-0.2, arm,psci-1.1 and so on. However, the same driver
can be used for all the versions by adding #define DT_COMPAT for
required version and #undef DT_COMPAT for default version.
Add support for PSCI cold reset, warm reset and cpu-on function IDs.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
If the optional hardware reset line is available, this change
will use that reset line to assert the uart module and bring
it out of reset state to use.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This is Intel's proprietary IP which controls individual module
reset signals. During each system driver initialization, these
reset signals will be used to bring module out of reset state.
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Device tree for Intel SoCFPGA Agilex5 initial bring up. This is the
first version of device tree which enable four cores SMP and basic
drivers that needed by 'hello_world' and 'cli' applications.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This is Intel's proprietary IP which supply the clock for all the
system peripherals. Clock manager is initialized only one time
during boot up by FSBL (ATF BL2) based on external user settings.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This is the initial Zephyr support for Intel SoC FPGA Agilex5 support.
Agilex5 has dual-core 64-bit ARM Cortex*-A55 and dual-core 64bit
ARM Cortex*-A76.
The Zephyr will need to be loaded by Intel Arm Trusted Firmware (ATF).
Agilex5 Zephyr boot flow:
FSBL:ATF BL2(EL3) -> ATF BL31(EL3) -> OS:Zephyr(EL1)
Intel ATF can be loaded from:
https://github.com/altera-opensource/arm-trusted-firmware.git
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Remove virtual esp32 board and replace it with the
real word boards:
- esp32_devkitc_wroom
- esp32_devkitc_wrover (with PSRAM option)
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Introduce dtsi files representing the
current portfolio of chips and modules
based on the:
- flash size
- psram size
- gpio count
- certification status
Update the boards dts files according
to which SOC/SIP they are using.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Introduce dtsi files representing the
current portfolio of chips and modules
based on the followint criteria:
- flash size
- psram size
- gpio count
- certification status
Update the boards dts files according
to which SOC/SIP they are using.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add `CONFIG_DEVICE_DEPS` to force two stage linking, otherwise the
following check means the test never runs:
```
if (TARGET zephyr_pre1)
add_dependencies(zephyr_pre1 check_init_priorities_output)
endif()
```
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Update the script to parse the new section naming. The ordering type
is converted from an integer to a tuple, which still compares correctly
due to the elementwise behaviour of tuple comparison.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
