This SoC has an external XCACHE controller for CPU0
instruction and data bus.
Add code to enable the data cache. Instruction cache
is already enabled by SystemInit.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Added gpio expander pca6416 support on the board, it use i2c bus to
expand IO ports.
Added GPIO test case overlay for the board.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Added gpio expander pca6416 support on the board, it use i2c bus to
expand IO ports.
Added GPIO test case overlay for the board.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The i.MX 91 Evaluation Kit (MCIMX91-EVK board) is a platform designed
to display the most commonly used features of the i.MX 91 applications
processor. The MCIMX91-EVK board is an entry-level development board
with a small and low-cost package.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
enable ctimer clock in board.c
set ctimer0 as ok for cm33_cpu0
set ctimer5 as ok for cm33_cpu1
test counter_basic_api case passed on cm33_cpu0/1
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Added device tree nodes in imx8mp_evk_mimx8ml8_a53.dts, and also
added board overlay in gpio_basic_api test case.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
According to the quick start guide of the FRDM-MCXC242 board, PTE0/PTE1
should be used for lpuart1. Enable and configure it in board dts.
Signed-off-by: Alexandre Rey <alx.rey@icloud.com>
Use TX and RX blocks on SAI for i2s speed test, by this way we can avoid
HW reworking.
Update Readme file and DMA channel configuration in overlay file to avoid
DMA channel conflict with other peripherals like UART.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
Add DT property to configure the LPSPI instance to use tristated output
instead of retained output when PCS is negated.
Turn on the config on a couple boards for test coverage.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Sets LinkServer as the default runner for the mimxrt1180-evk board,
as the board is configured for CMSIS-DAP by default.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The on-board S26HS512T 512M-bit HyperFlash memory is connected to
the QSPI controller port A1.
This board configuration selects it as the default flash controller.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Create common source code to use for supporting HyperFlash.
Rename 'FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME' to
'FLASH_NXP_S32_QSPI_SFDP_RUNTIME' as a common kconfig.
Add the 'max-program-buffer-size' property to use for
setting memory pageSize, instead of using
'CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE' for setting.
Add the 'write-block-size' propertyto use for setting
the number of bytes used in write operations, it also
uses to instead of the 'memory-alignment' property.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Add comment to DTS file about SRAM partitions similar to the RTXXX
series has comments.
Add also a doc section to the frdm_rw612 about this.
Also fix the section hierarchy of the frdm_rw612 doc, the header levels
were wrong since the wifi and bluetooth, and reference sections were
under the debugging section.
Group all the wireless connectivity info together.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
