Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `drivers` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Support for 8 dummy cycles in a single line RX transaction is required
for the standard JEDEC Read SFDP command. The SSI controller does not
support dummy cycles in Standard SPI mode, but the driver can simulate
those by just sending a dummy data byte.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Immediately finish an RX transfer when the RX FIFO overflow is
encountered and return the -EIO error code, which better indicates
the problem than -ETIMEDOUT that was returned previously in such
case.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- use separate code paths for TX and RX in ISR
- make sending of dummy bytes in the single line mode (Standard
SPI) more consistent so it can be easily extended
- use value 0 instead of 0xAA for dummy bytes as there is normally
no point in making noise one the MOSI line when only receiving
data (it can only be useful in debugging transfers)
- move all writing of data in the TX FIFO to ISR to avoid broken
transfers in the single line mode (where the clock stretching
is not available) when the driver is preempted right before it
enables interrupts
- use the TX FIFO start level also for transfers without data,
so that it's not possible that the TX FIFO gets emptied between
the writes of command and address fields in the single line mode
- add a few comments to explain better how transfers are handled
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
After the START task is triggered, the clock that drives the SSI core
needs some time to become ready. Before that, writes to SSI registers
may be unsuccessful. Add a loop that performs test writes to one of
the registers after the EXMIF peripheral is resumed to ensure that it
is fully operable.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- replace %d with %u in two error log message format strings
- add checks for maximum supported address length
- correct *_WAIT_CYCLES_MAX macros used in XIP handling routines
(although their values are valid, they belong to different SSI
registers)
- remove one unnecessary use of SPI_CTRLR0_WAIT_CYCLES_MASK
- remove doubled definitions of the XIP_CTRL register bit fields
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The utility may be used during development stage to get
ambiq platform specific timing parameters for mspi devices.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Add the MSPI controller support for apollo5x.
Add the MSPI controller to mspi API test.
Updated west.yml for hal updates.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
1. Moved ambiq specific macro to mspi_ambiq header.
2. Always fill rx&tx dummy settings regardless of transfer direction.
3. Add the CONFIG_MSPI_* macro for optional features.
4. Fixed the ID read process and add k_sleep during busy_wait in
atxp032 driver.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Add a generic driver for MSPI controllers based on the DesignWare
SSI core. With small vendor-specific adaptations covering integration
details, it should be possible to use the driver for various devices.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
DT_INST* should be used in MSPI_CONFIG or device tree value capture
will fail sliently and fall back to defaults.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
REG_X_BASEADDR will be removed from all hal files.
This forces the use of the peripheral base address
Define MSPI_PORT macro for chip drivers
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
The Ambiq MSPI controller is implemented using the MSPI bus API.
The hardware supports up to 48MHz octal SDR with XIP, scrambling and
hardware command queue features.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Add bus emulator support for MSPI and the MSPI controller emulator.
The mspi_emul.c not only serves as an emulator but also provides an
example implementation of the MSPI API. It does not actually do anything
other than validating parameters and forwarding transceive request back
to the device driver emulators.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
The MSPI(multi-bit SPI) is provided as a generic API to accommodate
advanced SPI peripherals and devices that typically require command,
address and data phases, and multiple signal lines during these phases.
While the API supports advanced features such as XIP eXecute In Place
and scrambling, it is also compatible with generic SPI.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
