This commit should deal with
fixing the way USB_MCTLR_REG
is zeroed in order to disable
the USB controller along with
its tranceiver.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
This commit should deal with updating
the way USBD was handling the DMA
engine. Based on the #73803 request
DMA should be handled via the DMA
driver API class and not directly.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
When device was resumed from sleep OUT endpoints were most
likely not enabled due to condition that checked pending transfer.
Configured OUT endpoints should be enabled (ready for RX)
if they were enabled by interfaces.
Now separate bit field enabled is added and check to
see if OUT endpoint should be ready for reception after
sleep is done.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Callback with USB_DC_EP_DATA_OUT was called directly from
interrupt handler (handle_ep0_rx()) while rest of the interrupt
conditions were not checked yet.
Some interfaces started next transfer directly from this callback
resulting in case where TX endpoint was still marked as busy
and transfer was eventually abandoned.
Now message is sent from all affected endpoints after every USB
pending interrupt is handled.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Switching from write to read on EP0 is done when data is
transmitted.
Additionally receiver is enabled when NAK is created in
response to OUT token. This may happen when host sent
ZLP before everything was transmitted.
This case flushed receiver FIFO which could lead to
setup packet corruption.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Add support for automatic control of PLL for USB subsystem.
This utilized virtual USB clock present in clock control.
USB driver enables PLL when device is attached or USB
sends resume signaling.
PLL can be turned off (if application does not requested it)
when device is detached (application request)
or USB host sends suspend request.
When VBUS is not present or application did not started USB yet
PD_DOMAIN_SYS is also not acquired that allows for deep
sleep. When USB is active deep sleep will never be activated.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
When EP0 was disabled EP0 was setup to ignore setup and
out packets.
In usb_dc_ep_enable() function mask was never cleared.
It resulted in USB stop functioning after application
disabled endpoint (usb_disable()) and then tried
to enable usb again.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Implement absolute minimum necessary to get Buffer DMA working. Require
Data Cache to be disabled if DWC2 OTG has DMA enabled because the stack
does not currently guarantee cache line alignment for allocated buffers.
Set EPENA bit before disabling IN endpoints because it seems to be
necessary in Buffer DMA mode (without EPENA the wait for INEPNAKEFF does
time out). Setting EPENA should have no impact on Completer mode
operation (where EPENA is not necessary for INEPNAKEFF to trigger).
Programming Guide recommends programming SUPCnt to 3, but the only
advantage would be to be able to tell how many back-to-back SETUP packets
were received if there was no more than 3 back-to-back SETUPs. This
information doesn't seem to be useful. The disadvantage is that the
buffer needed for receiving SETUP packet must be able to hold SUPCnt
multiple of 8 bytes. Use SUPCnt 1 so the 8 bytes buffer is enough.
Make sure to clear StsPhseRcvd interrupt bit in Buffer DMA mode because
the DMA seems to prevent the SETUP Phase Done interrupt from triggering
if StsPhseRcvd is set. Clearing this bit doesn't seem to be necessary in
Completer mode. This bit is set on control transfers with data stage
from host to device.
Both Buffer DMA and Completer mode operation on nRF54H20DK was verified
using USB2CV Chapter 9 Tests and MSC Tests with Mass Storage sample.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Do not use sys_clear_bits() followed by sys_set_bits() on DCTL register
to avoid writing to DCTL register twice - first with zeroed out address,
and then with the new address. Change the code to write the address in
one DCTL register write.
Do not use sys_set_bits() to set test mode, but rather prepare the
correct value first.
Set DCFG and GUSBCFG registers in one go. There is no point in reading
back the value or doing multiple subsequent writes to these registers.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
udc_mcux_ehci is based on the MCUX USB controller driver
(usb_device_ehci.c); udc_mcux_ip3511 is based on the
MCUX USB controller driver (usb_device_lpcip3511.c);
add related Kconfig and CMake; include the usb_phy.h path in
modules/hal_nxp/usb/CMakeLists.txt because udc_mcux.c use it;
add related macros to usb_device_config.h;
update CMakeLists for udc_mcux_ehci and udc_mcux_ip3511.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Add Kconfig option for enabling high speed USB support for the native posix
USB controller driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Release buffer allocated in dwc2_ctrl_feed_dout() on endpoint deactivate
to prevent the buffer from leaking on USB stack disable.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
According to the Zephyr documentation, the number of bytes available
for read should be returned if the input data and length parameters are
NULL and zero, respectively. This commit corrects this behavior.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Since the fifo control register and ready bit are checked in ISR
function, this commit locks IRQ when accessing these registers to
prevent racing conditions.
Tested with: Google spikyrock project
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
This commit addresses some issues during the extended endpoint(ep
number is larger than 4) access. There are enable and ready bits for
each endpoint on the IT82xx2 chip. The transaction completion should be
determined by the ready and enable bits of the corresponding endpoint.
Additioinally, for non-control endpoint, the FIFO control register is
selected before writing data and cleared when the IN transaction is
completed. When an IN token interrupts, the FIFO control register
should be checked if it's selected to prevent fake tokens.
Tested with: Google spikyrock project
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Make sure to feed control OUT endpoint with at least 8 bytes buffer to
make it possible to always receive SETUP data. This solves the assertion
failure in net_buf_add() called inside dwc2_handle_evt_setup() when a
host decides to start new control transfer immediately after it has
issued control transfer with Data Stage from host to device with wLength
less than 8.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add support for GPIO controlled disconnect pullups. This is used in F1
based devices, copied from the legacy driver.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
On nRF54H20DK the USB PHY is powered from VBUS. When the USB cable is
not connected, the PHY is not powered and the PHY clock disappears.
Because the GOUTNAKEFF and INEPNAKEFF can only ever be set when PHY
clock is active, the waits for these bits do timeout if cable is
disconnected. Workaround the issue by aborting the wait if vendor quirk
indicates that PHY clock has abruptly vanished.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add UDC driver for IT82xx2 SoC. This commit passes tests with
1. samples/subsys/usb/cdc_acm/
2. samples/subsys/usb/console/
3. The extend endpoint test with CDC ACM tool
4. USB suspend/resume detection
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Flushing TxFIFO is racing with actual use of the TxFIFO. The software
controls only one side of the race (flush trigger) while the host
controls the other side. Therefore, locking interrupts before flushing
TxFIFO is not protecting against the race condition.
Disable the endpoint on dequeue to make sure that TxFIFO flushing won't
conflict with host actions (because the endpoint would be forced to NAK
the IN tokens before the TxFIFO is flushed).
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Do not set NAK bit again for endpoints that already have NAK bit set.
Do not wait for OUT endpoint 0 disable because it cannot be disabled by
application (DOEPCTL0 EPDis bit is Read-Only).
Disable endpoints before disabling interrupts because it is necessary to
handle RXFLVL interrupt (in Slave mode) for GOUTNAKEFF to become active.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
cbprintf_package complains about char usage for %p
string argument and suggests void * usage.
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
DWC2 documentation unfortunately assigns somewhat confusing semantics to
endpoint "enable"/"disable" and "activate"/"deactivate". The Zephyr USB
device stack endpoint enable/disable refers to DWC2 activate/deactivate.
The DWC2 endpoint enable/disable actions can be loosely referred to
Zephyr USB stack enqueue/dequeue.
Rename the functions and rework internal working to match DWC2
Programming Guide. This makes endpoint halt work as expected by the
stack and therefore fixes all classes that rely on correct STALL
handling. Most notable STALL user is the Mass Storage class.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
DWC2 programming guide mentions that SETUP can only be processed by
application after DOEPINTn.SETUP interrupt. Not respecting this
requirement makes setting Global OUT NAK hang while waiting for
GOUTNAKEFF interrupt until the host starts next control transfer.
Global OUT NAK is necessary if the application ever wants to properly
cancel any ongoing transfer.
Change the processing to comply with the programming guide.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
On USBHS, we cannot access the DWC2 register until VBUS is detected and
valid. Kernel event API is used to block if a valid VBUS signal is not
present when the user tries to force usbd_enable().
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The NUMDEVEPS field provides the number of endpoints in addition to the
control endpoint. It is used to iterate over GHWCFG1 register value to
get correct number of configured IN/OUT endpoints. To get it correctly,
we need to use it internally as number including control endpoint.
Interpretation of INEPS misses +1 because value 0 means 1 IN endpoint
and so on.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Although we can get the number of configured OUT and IN endpoints and
endpoint capabilities from the DWC GHWCFGn registers, we need to
configure the number of endpoint configuration structs at build time. On
some platforms, we cannot access the hardware register at pre-init, so
we use the GHWCFGn values from the devicetree to provide endpoint
capabilities. This can be considered a workaround, and we may change the
upper layer internals to avoid it in the future.
Also, add a new vendor quirk to fill in platform-specific controller
capabilities.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Rework and rename vendor quirks to better reflect where they intended to
be called. Number of quirks probably not final and will be trimmed
later.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Move most of the controller initialization to a separate function called
during udc_enable(). This allows us to add support for the platform
where the device controller is only available when VBUS is present and
the PHY is powered.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
udc_init() only initializes and enables the USB regulator. This is
enough to detect VBUS changes, the USB controller is enabled in
udc_enable(). Deinitialization happens correspondingly in reverse order.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
For the simple events, do not check whether the device driver and stack
are marked as initialized. USB device notification will reschedule
delivery if the stack is not yet marked initialized.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Pass DIEPTXF address instead of value to sys_read32() to prevent bus
fault when debug logging is enabled.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
- If the peripheral is OTG_HS with ULPI, enable the OTG_HS ULPI clock
- The constant has a slightly different name on stm32h7
- Otherwise, if the peripheral is OTG_HS:
- Disable the OTG_HS ULPI clock in sleep/low power mode,
- If the peripheral is OTG_HS with PHYC[1], enable the PHYC clock.
- Otherwise, if the peripheral is OTG_FS[2] on stm32h7, also disable the
OTG_FS ULPI clock in sleep mode (in the device/ driver, this is done in
usb_dc_stm32_init()),
[1]: Internal HS PHY in stm32f7x2xx and (some) stm32f730xx
[2]: "OTG_FS" on stm32h7 is really just another OTG_HS peripheral, but
without any way to actually connect a HS PHY
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
DWC USB 2.0 HS OTG Controller sets USB Reset interrupt after Reset
signalling starts, but before the High-Speed Detection Handshake. This
allows software to perform most of the reset handling even before the
connection speed is known. The device controller indicates High-Speed
Detection Handshake result is available in DSTS register by setting
Enumeration Done interrupt.
USB stack expects that the connection speed is known immediately after
UDC_EVT_RESET is submitted. Due to this expectation, it is important to
submit UDC_EVT_RESET only after Enumeration Done interrupt to prevent
the USB stack from reading (and storing) actual device speed before
it is known.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
During a control read transfer host is able to start status stage as
soon as it receives last data packet. The time between last data packet
and status stage can be approximately 1 us at High-Speed and 8 us at
Full-Speed (exact timing depends on host but it is mostly constrained by
bus turnaround time).
With sufficient interrupt latency it is therefore possible that both
IEPINT (raised at end of Data Stage) and RXFLVL (raised at Status Stage)
would be set when dwc2 interrupt handler reads GINTSTS register. When
device is operating at High-Speed, the latency introduced by UART logger
backend is enough to trigger this condition. If the RXFLVL is handled
before IEPINT the stack will trigger "Cannot determine the next stage"
error.
Handle IEPINT before RXFLVL to make the handler immune to increased
interrupt latencies.
Co-authored-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
USB_NATIVE_POSIX dependencies were partially broken for
native_sim as the option was duplicated in the boards
defconfigas.
Let's not define it also in the board Kconfig.defconfig
but instead default it to y in its main definition if
building for either native_posix[//64] or native_sim[//64]
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Mass Storage enumeration failed because udc_stm32_ep_mem_config() was only
increasing priv->occupied_mem on endpoint enable, and not decreasing it on
endpoint disable. Fix the issue by decreasing priv->occupied_mem
on endpoint disable.
Signed-off-by: Arne Bohnsack <arne.bohnsack@draeger.com>
Updates the linker script fragments under 'drivers' to use
Z_LINK_ITERABLE_SUBALIGN for the subalignment instead of
a hardcoded value of 4.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Submit USBFSOTG_EVT_XFER on halt clear to allow queued
transfers to execute as soon as endpoint STALL is cleared.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
When running the cdc_acm demo on a board with an external ULPI
phy, the device is unable to enumerate:
usb 1-1.8.3.1: new full-speed USB device number 51 using ehci-pci
usb 1-1.8.3.1: device descriptor read/64, error -32
usb 1-1.8.3.1: device descriptor read/64, error -32
the console shows:
[00:00:00.001,000] cdc_acm_echo: Wait for DTR
[00:00:00.007,000] usb_cdc_acm: Device suspended
[00:00:00.902,000] usb_cdc_acm: Device resumed
[00:00:00.902,000] usb_cdc_acm: from suspend
[00:00:25.526,000] usb_cdc_acm: Device suspended
By not disabling the ULPI clock in low power, the usb enumeration
is working and we can run the cdc_acm demo. While touching
this code, add some comments to clarify the macro nesting.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Magic constants throughout the code made this difficult to reason about,
especially with two different units of measurement (bytes and words) at
play.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The RX FIFO size is in words, so needs to be subtracted from the total
memory size *after* it's divided by 4.
Fixes#70789.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
1. Configure 'core-clock' to 192MHz to generate necessary 48MHz
2. Support workaround to disallowing ISO IN/OUT EPs to be assigned
the same EP numbers
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
The driver cannot handle OUT transactions for an endpoint with an
MPS smaller than 64 bytes. To solve the issue, we will not use one
fixed value, EP_MPS, but instead use the actual MPS of an endpoint,
ep_state->ep_mps.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
There is default 15K-ohm pull-down for USB controller.
To disable the default pull-down to avoid signal contention in GPIO mode.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
When usb middleware sends a start of frame notification to this driver,
call status_cb with USB_DC_SOF.
Signed-off-by: James Zipperer <jzipperer@fb.com>
A Zero Length Packet can be used by higher layer stack to discover when
an endpoint is being processed by the host. An example of this was
introduced as part of 0127d000a2 ("usb: device: cdc_acm: Use ZLP to
detect initial host read") in the CDC ACM class.
Not invoking the callback for ZLPs results in the higher layer stack not
being informed when the packet is consumed. This manifests as a CDC ACM
USB-IP device that cannot transmit to the host while being able to
receive from the host.
Signed-off-by: Abe Kohandel <abe.kohandel@gmail.com>
This commit partially reverts a change which was introduced in the
previous commit 5b9a0e5456.
usb_dc_ep_start_read() should also be called on transfer endpoints
like it has been before, otherwise the endpoint will not be armed
after it has been reconfigured.
Signed-off-by: Manuel Aebischer <manuel.aebischer@netmodule.com>
Like the stm32H5, stm32u5 usb device has an independent
power supply, but control bit is PWR_SVMCR_USV.
The control bit for the stm32H5 is PWR_USBSCR_USB33SV (no change)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When reconfiguring a previously used endpoint, it may still be locked
when a write was taking place when e.g. the host application crashed.
The call to udc_rpi_cancel_endpoint seems to do a proper cleanup of
the endpoint, i.e. the write semaphore will be released.
Fixes#66723.
Signed-off-by: Manuel Aebischer <manuel.aebischer@netmodule.com>
There are some issues with the extended endpoint settings. The incorrect
setting leads to the chip being unable to respond with NAK when the host
polls the extended endpoint for data transfers. Additionally, the controls
for the extended endpoint's ISO and PID data sequence are also incorrect.
This commit addresses these issues to properly support extended endpoint
transactions.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
There are two registers that control the selection of one FIFO as data
buffer for 15 endpoints (ep1-ep15). Both registers should be configured
before sending and receiving data. Additionally, there was an issue with
the corresponding FIFO index setting in the 'usb_dc_ep_read_continue'
function, which has been addressed in this commit.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
The stm32H5 mcu has an independent USB supply to be enabled
at init with LL_PWR_EnableVDDUSB function like the stm32U5 serie.
Both series have PWR_USBSCR_USB33SV bit in their USBSCR POWER reg.
and other series all have PWR_CR2_USV bit in their CR2 POWER reg.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The previous behaviour led to an issue where we already expected data1
on the first transfer instead of data0. The DesignWare USB DC actually
implements the same behaviour. Also, the next_pid flag has to be reset
on setting up the endpoint.
Fixes#66283.
Signed-off-by: Manuel Aebischer <manuel.aebischer@netmodule.com>
The driver currently supports only dedicated FIFO mode (with
dynfifosizing if enabled). Control, bulk and interrupt transfers are
supported, isochronous transfers are not yet supported. The driver
accesses controller registers using sys_io.h, but for debugging purposes
one can get a register map from the driver's config, similar to the
usb_dc_dw.c driver.
Initial support also has vendor quirks for the STM32F4 SoC family.
Tested on NUCLEO-F413HG.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Use new common header and remove usb_dw_registers.h.
No functional changes, only renaming of registers and field identifiers.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This header is based on drivers/usb/device/usb_dw_registers.h and
describes registers of the DWC2 controllers IP and is intended for use
in both device controller drivers and a host controller driver. The
difference to usb_dw_registers.h is that this header does not confuse
offsets with bit positions, contains all the definitions required for
device mode, has register and bit field names identical to the databook
and no annoying underscores.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Change k_heap_alloc wait duration to K_NO_WAIT in kinetis USB driver,
since the usb_dc_ep_configure function may be called from an ISR
context, where only K_NO_WAIT would be allowed as a duration for this
function.
Fixes#66507
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Isochronous endpoint issue with USB drivers on STM32G491
we setup an isochronous endpoint and are having an issue
where every other frame sends the desired data sandwiched
between garbage data.
For isochronous the parameter ep_kind into the fonction :
HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress) must be PCD_DBL_BUF.
The parameter pmaadress (EP address in The PMA) is like that:
EP address in The PMA: In case of single buffer endpoint
this parameter is 16-bit value providing the address
in PMA allocated to endpoint.
In case of double buffer endpoint this parameter
is a 32-bit value providing the endpoint buffer 0 address
in the LSB part of 32-bit value and endpoint buffer 1 address
in the MSB part of 32-bit value.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Submit resume event after remote wakeup (resume) signalling is
initiated. Handle it same way as in the usb_dc_nrfx driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
the FIFO Rx need to have a Minimum memory to works
distributed the rest of the ram_size memory between
the different TX FIFOs except the first which is
a control endtype with max data payload of 64 bytes
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Code uses local RAM buffer to properly handle the case where provided
USB transfer TX data is not in RAM.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
ep_ctrl and ep_trans_type is not used inside it82xx2_usb_dc_isr, this
triggers a compile warning. Move these variables to a smaller scope.
Signed-off-by: Ting Shen <phoenixshen@google.com>
Use MDK directly instead of via USBD HAL to not mix direct register
accesses with USBD HAL. In my opinion this change is not really
necessary but reviewers are strict about consistency.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
There is no point in setting the feeder or consumer at runtime. The time
saved due to not checking conditions on each transaction is smaller than
the additional cost of calling function via pointer.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Do not enable nor disable endpoint done interrupts at runtime because it
is not necessary. Simply keep all relevant interrupts enabled when USBD
is active and disable all interrupts when USBD is disabled.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Ensure strict order within interrupt processing to eliminate workaround
in IN transfer acknowledged handler. EPDATASTATUS and DMA done events
are processed in a way that eliminates the possibility for race condions
between interrupt handler and host IN tokens.
Store last started DMA endpoint and use it in common handler for all DMA
finished events. Unify use of ep dma waiting variable because atomics
only make sense if all accesses are through atomic functions - here the
accesses are guarded with critical section.
Do not disable SETUP interrupt when DMA transfers data on endpoint 0 but
simply postpone handling if currently active DMA is on endpoint 0.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
There is no point in calling an empty function on every single DMA
transfer start. While the empty function is just BX LR the fact that is
is called on every DMA transfer makes its impact visible. This change
improves CDC ACM echo throughput by approximately 2%.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Early DMA process handling actually decreases performance in real world
scenarios because real world scenarios tend to be CPU bound. Moreover
the actual optimization is questionable because DMA semaphore can only
be released after the respective endpoint end event is handled. Remove
early DMA processing altogether and only check pending DMA at the end of
interrupt handler.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Rely on semaphore to serialize access to DMA instead of busy looping
after triggering DMA. With this change Ozone Code Profile generated with
J-Trace Pro on nrf52840dk_nrf52840 board running headphones microphone
sample shows following Load changes (trace data was reset once playback
and recording started and percentages were taken when memcpy reached
200 000 Run Count):
* usbd_dmareq_process() from 17.16% to 2.24%
* memcpy() from 9.37% to 8.36%
* nrf_usbd_common_irq_handler() from 8.89% to 10.88%
Mark nrf_usbd_common_stop() as static because the caller must acquire
DMA semaphore before calling this function and the only place where it
is used is already acquiring the semaphore.
Disable EP0 SETUP interrupt when there is active DMA on EP0 to eliminate
the need for aborting DMA on EP0. This code path should not really
happen in real life though because hosts must not issue new SETUP before
a relatively long timeout (at least 50 ms).
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Rename local usbd copy from nrfx_usbd to nrf_usbd_common and use it in
both USB stacks. Renaming header to nrf_usbd_common.h allows breaking
changes in exposed interface. Mark all doxygen comments as internal
because local usbd copy should not be treated as public interface
because we are under refactoring process that aims to arrive at native
driver and therefore drop nrf_usbd_common in the future.
Use Zephyr constructs directly instead of nrfx glue macros.
No functional changes.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Move the syscall_handler.h header, used internally only to a dedicated
internal folder that should not be used outside of Zephyr.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The k_mem_block structure has been obsolete for some years with
a few loose ends still remaining. As its usage in the usb_dc_mcux
codebase was confined to needing its "void *" pointer field, it
was simple to enough to hoist that field to remove another loose end.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Prevent use of isochronous endpoints as bulk and/or interrupt endpoint.
The issue was observed when trying to use 4 CDC ACM instances where the
4th instance would claim the isochronous IN endpoint 0x88 to be bulk.
Because the isochronous endpoints cannot respond with handshake packet
the iso endpoints cannot be used as bulk or interrupt substitue.
Properly fail endpoint check and therefore make 4 CDC ACM instances not
enumerate at all because the hardware has endpoints that only allows up
to 3 CDC ACM instances.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
