Use timeout mechanism instead of unbounded loop during enabling ITIM32
module which source clock is LFCLK (32KHz).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Qemu when running more than one processor has a known synchronization
bug where counter values read from the HPET (notionally a single
global device) can be seen going "backwards" when read from different
CPUs.
There was a pre-existing workaround in the ISR that knew about this,
but the problem can crop up anywhere the counter value is used. In
particular I caught it aliasing with the "max_ticks" computation in
z_clock_set_timeout(), where it would cause a rollover and the
resulting negative comparator value would result in no end of
hilarity.
Wrap all access to the counter register with a counter() inline that
(when the workaround is enabled) forces the result to be monotonic by
clamping it to a minimum of one more than the previously read value.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This include make possible to use the arm_arch_timer on
platform such as Cortex-A9 or Cortex-R7 which has support for
ARM Global Timer.
The global timer is a 64 bit incrementing counter, memory-mapped
in the private memory region.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The count register is 64 bits, but we're a 32 bit CPU that can only
read four bytes at a time, so a bit of care is needed to prevent
racing against a wraparound of the low word. Wrap the low read
between two reads of the high word and make sure it didn't change.
Fixes#31599
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
idle is only considered in other timer implementations if ticks ==
K_TICKS_FOREVER but in arm_arch_timer. Just fix it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
TICKLESS_CAPABLE is now selectable only and without prompt, so remove it
from _defconfig files and select it directly by the timer.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
z_timer_idle_enter is declared only when CONFIG_TICKLESS_IDLE is
selected. This function is not implemented anywhere, but the only
driver including this header is not TICKLESS_CAPABLE. So, no undefined
reference will happen.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Due to clock discrepancy, busy waiting for 15us was not covering for
half tick in certain cases. Busy wait runs from HF clock source.
Increased to 19us to cover it. Anyway, this case is hit very rarely,
only when there was aborted, not-cancelled compare value that was
about to expire. Because of that, increase shall not impact the
performance.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
For a while now, we've had two APIC drivers. The older was preserved
initially as the new (much smaller, "new style") code didn't have
support for Quark interrupt handling. But that's long dead now. Just
remove it.
Note that this migrates the one board using this driver (acrn) to
CONFIG_APIC_TIMER instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
As timer interrupt is level triggered, we need to mask it before leaving
ISR or it will be delivered again.
Also, Xen automatically masks timer interrupt when it injects IRQ to
a guest, so we need to unmask it again, when setting new timeout.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is about the it8xxx2 timer driver.
We use the timer 5 as system timer for count time,
so the timer interrupt is trigged by it.
Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
Add a new test for k_busy_wait and cpu_hold
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Signed-off-by: Wolfgang Puffitsch <wopu@demant.com>
In native_posix and nrf52_bsim add the cpu_hold() function,
which can be used to emulate the time it takes for code
to execute.
It is very similar to arch_busy_wait(), but while
arch_busy_wait() returns when the requested time has passed,
cpu_hold() ensures that the time passes in the callers
context independently of how much time may pass in some
other context.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
When tickless mode was disable, sys clock timeout handler was calling
public API function for setting new compare value. Public API function
asserts when chan 0 is used which is reserved for system clock.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Added clearing of CC event which may occure due to previous
CC value which was closed to current counter value.
Fixed int_mask initialization.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Fix TIMER0 and RTC0 being selectable when using out-of-tree Bluetooth
controller.
Generalize the Kconfig to have the features that use the HW peripheral
select them as reserved to make the dependencies more manageable.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
- Remove SYS_ prefix
- shorten POWER_MANAGEMENT to just PM
- DEVICE_POWER_MANAGEMENT -> PM_DEVICE
and use PM_ as the prefix for all PM related Kconfigs
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Extended nrf_rtc_timer driver to expose API for using RTC for
other purposes. System timer is using one compare channels,
other channels may be used through this API.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This adds support for GRLIB GPTIMER general purpose timer used in
LEON3/4/5 systems.
One of the GPTIMER subtimers is used to generate periodic interrutps
for announcing ticks. Another subtimer is used as upcounter for the
cycle_get_32() service.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Replaces all existing variants of value clamping with the MIN and MAX
macros with the CLAMP macro.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
The HDA wall clock timer is a 64 bit timer with 64 bit compare
registers, but it's being used from a 32 bit CPU. Writing the
comparator piecewise with a 64 bit C assignment will write the low
dword first, opening the possibility that the hardware will see time
go "backwards" and trigger an interrupt incorrectly.
Disable the enable bit while setting the comparator.
Found by inspection. In practice this will be very rare, and spurious
timer interrupts are supposed to be benign anyway (though they can
result in timeout expirations being misaligned to ticks, which might
be surprising to applications). Best to get it right.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Added configuration for approach to starting system clock source.
There are 3 options: no wait, wait untill available, wait until
stable.
Added support for those modes in clock control driver which handles
low frequency source clock.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Use setting from devicetree to drive the default setting for
CORTEX_M_SYSTICK. We update the dts files to default systick to be
enabled since the major of cortex-m platforms utilize it by default
(except on Nordic SoCs, TI CC13x2/CC26x2 and MEC1501 in which we
default to disabled).
Fixes#25299
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This code had one purpose only, feed timing information into a test and
was not used by anything else. The custom trace points unfortunatly were
not accurate and this test was delivering informatin that conflicted
with other tests we have due to placement of such trace points in the
architecture and kernel code.
For such measurements we are planning to use the tracing functionality
in a special mode that would be used for metrics without polluting the
architecture and kernel code with additional tracing and timing code.
Furthermore, much of the assembly code used had issues.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Marking as unused (ARG_UNUSED) the parameter device in the
initialization function z_clock_driver_init when it is not used.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
There is nothing wrong with instance numbers and they are
recommended for use whenever possible, but this is an API
design problem because it's not always possible to get nodes
by instance number; in some cases, drivers need to get node
identifiers from node labels, for example.
Change these APIs (which are not yet in any Zephyr release)
to take node IDs instead of instance IDs.
Fixes: #26984
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This set of functions seem to be there just because of historical
reasons, stemming from Kbuild. They are non-obvious and prone to errors,
so remove them in favor of the `_ifdef()` ones with an explicit
`CONFIG_` condition.
Script used:
git grep -l _if_kconfig | xargs sed -E -i
"s/_if_kconfig\(\s*(\w*)/_ifdef(CONFIG_\U\1\E \1/g"
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Adapted driver to clock_control changes (usage of onoff manager).
Since timer is permanenty requesting the clock, it is using API
dedicated for that: z_nrf_clock_control_lf_on().
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
When checking the absolute value of cycles set to the comparator
use the MAX_CYCLES instead of MAX_TICKS.
The commit changes function names and comments to make it clear
where ticks (system ticks) and where RTC cycles are used.
Fixes#26701
Signed-off-by: Pawel Dunaj <pawel.dunaj@nordicsemi.no>
K_FOREVER/INT_MAX number of ticks needs delay cycles value of
maximum order and exceeds 'int32' range.
The typecast to 'int32' results in wrongly evaluating the value
as less than 'MIN_DELAY' and chooses 'MIN_DELAY' over the actual
delay cycles.
Cap the 'MAX_TICKS' to INT32_MAX.
fixes: #26632
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
The front side bus interrupt delivery feature is a somewhat obscure
part of PC history (in some sense a presaging of MSI interrupts) that
we don't use.
But it's part of the spec, works on hardware, has precedence over the
"legacy" interrupt routing feature we do use, and can be legally
enabled by firmware.
Disable at init time.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Avoid reading LPTIM counter four times instead of three when second
read doesn't give same value. Use common code, avoid volatile for
local vars.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
The HPET timer was hard-coded to support only edge triggering
interrupts. This adds the necessary bits to enable level
triggering for the timer.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When setting a timeout K_TICKS_FOREVER,the lptimer clock is stopped
(no reset of the lptim).
Then is the lptim possibly re-started when another source asks for.
The lptim clock must then be re-started and continue counting.
This is the case when wakeup from sleep mode, for example.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The LPTIM driver is supposed to be only available when the SoC is
allowed to enter power sleep mode, as described in commit f30f5fff72
("drivers: timer: lptim is [EXPERIMENTAL] for stm32 soc series only").
For that it should depends on SYS_POWER_MANAGEMENT (which gates the
SYS_POWER_SLEEP_STATES and SYS_POWER_DEEP_SLEEP_STATES options) instead
of DEVICE_POWER_MANAGEMENT.
Fixes#25989
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Some ticks are counted additionally when the autoreload
interrupts were too close together.
This patch improve the counts of the clock cycle.
lptim_fired worked badly in particular because the flag ARRM
was not raised when the interrupt was forced.
Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
If ticks is K_TICKS_FOREVER the register autoreload isn't set.
So, on the next call to the z_clock_set_timeout function
the wait for the flag ARROK will be infinite.
Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
We don't need to reset backup domain to set LSE clock source.
It's dangerous to reset backup domain, it removes:
- RTC configuration
- backup registers
- RCC Backup domain control register
Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
Activation of the LPTIMER is valid for SLEEP MODE only
The choice of the lptim clock source is STM32_LPTIM_CLOCK
set the LSE in first position to have as default value
Signed-off-by: Francois Ramu <francois.ramu@st.com>
based on PR#25412
Some kernel tests use `CONFIG_TICKLESS_KERNEL=n` with
`CONFIG_SYS_CLOCK_TICKS_PER_SEC=1` to detect when a test runs longer
than 1 second. These tests break if a tick is announced every time a
timeout occurs. Only announce if the measured duration since the last
tick is at least the duration of a tick.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
set the min and max values of the given ticks from 0
to LPTIM_TIMEBASE which is the full register value
In case the timeout is FOREVER, then lptimer is stopped
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The current value of the counter must not be added to the accumulator.
It will be added when calling z_timer_cycle_get_32.
Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
When the tickless kernel isn't used, we don't want to wait for ARROK.
This wait can be endless.
Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
This reimplements z_timer_cycle_get_32() so it works
when IRQs are locked and solves the hung
k_busy_wait() problem.
Fixes#23622.
Signed-off-by: Jakub Cebulski <jcebulski@internships.antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Co-authored-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
The weak implementation returns 0 for all operations without doing
anything, which incorrectly suggests that an operation like
device_get_power_state() returned an accurate description of the
system clock power state. Return -ENOTSUP instead.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
If timeout is being overwrite exactly when previous one is expiring
then hardware event was cleared correctly but interrupt was already
triggered. Interrupt routine was assuming that compare event is set
and proceed with that assumption. However, in that corner case when
compare event was overwritten and event was cleared, that was not the
case.
As the outcome, timeout could be triggered prematurely. Fixed by
clearing pending interrupt after handling previous compare value.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
* still need to clear IP bit in timer irq handler
* last_time should be aligned to ticks, old code will miss some
cycles which are about (curret_time - last_time) % CYC_PER_TICK
* in timeout set, shorten the delay needed when tick is 0, this
will improve the response of timer irq
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
the pulse triggered timer irq doesn't work for all targets. In
iotdk, we found the clear of IP bit will clear int request
when elapsed called in thread context. So come back to level
triggered way which is supported in all targets, and use the sw
triggered irq to remember the irq request which may be cleared
in non timer int handler.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
* rename overflow_cyc to overflow_cycles for better understanding
* use MIN macro to replace if .. else ..
* typo fix in comments
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
This adds the calls to read_timer_{start,end}_of_tick_handler()
to mark the start and end of ISR which will be used to display
the time spent in ISR with benchmarking tests.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Some kernel tests use `CONFIG_TICKLESS_KERNEL=n` with
`CONFIG_SYS_CLOCK_TICKS_PER_SEC=1` to detect when a test runs longer
than 1 second. These tests break if a tick is announced every time a
timeout occurs. Only announce if the measured duration since the last
tick is at least the duration of a tick.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Use device tree provided configurations for arm architecture timer
PPIs.
This fixes issue of timer ppi not working on most hardware where
edge-triggered PPI are not supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
INLINE is a very common macro, just like MAX or MIN.
Defining it always can easily collide with libraries or
application headers.
And option would be to add a ifdef guard around it,
But it was used in only 1 place in Zephyr, instead
of keeping it just for that, remove it.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
referring the ARM's Systick driver, we did the following improvements:
* use 31 bits of 32-bit counter to avoid the rare but possible
overflow of elapsed(). If 32 bits val are used, elpased() may
return a wrong value. then wrong HW cycles.
* two ways to update the correct cycles
- through systick timer irq
- when systick timer irq cann't be handled because of irq
locked/disabled, call z_timer_cycle_get_32->elapsed to update
the correct cylces. no more than one counter-wrap is allowed.
* if elapsed() is not called too long (more than one counter-wrap) from
systick tiemr irq or from z_timer_cycle_get_32. The lost of HW cycles
is unavoidable.
* some detailed discussion can be found in #24332
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Use NODELABEL macros rather than DT_INST as this driver is so far
limited to support of LPTIM1 instance.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
User reported a flaw in the current algorithm which fails when Zero
Latency Interrupts (ZLI) are used. Ported algorithm from
counter_nrfx_rtc.c which covers all cases. Algorithm is lockless so
no distinction for ZLI is needed.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Replace various drivers and soc code that use DT_CAVS_ICTL_BASE_ADDR
with DT_REG_ADDR(DT_NODELABEL(cavs0)).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In the ARM Cortex-M architecture implementation, the concepts of
"exceptions" and "interrupts" are interchangeable; whereas, in the
Cortex-A/-R architecture implementation, they are considered separate
and therefore handled differently (i.e. `z_arm_exc_exit` cannot be used
to exit an "interrupt").
This commit fixes all `z_arm_exc_exit` usages in the interrupt handlers
to use `z_arm_int_exit`.
NOTE: In terms of the ARM AArch32 Cortex-A and Cortex-R architecture
implementations, the "exceptions" refer to the "Undefined
Instruction (UNDEF)" and "Prefetch/Data Abort (PABT/DABT)"
exceptions, while "interrupts" refer to the "Interrupt (IRQ)",
"Fast Interrupt (FIQ)" and "Software Interrupt/Supervisor Call
(SWI/SVC)".
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
clock-generator is a normal property. To access it we should use
DT_INST_PROP(0, clock_generator) and not DT_INST_CLOCKS_CELL().
Fixes: #24399
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
sys_clock_disable now is only called in sys_reboot.
This API is outdated, no need to implement it and
there is a weak version.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Commit 7832738ae9 ("kernel/timeout: Make timeout arguments an opaque
type") changed the forever value for timer drivers to K_TICKS_FOREVER
from K_FOREVER.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This adds the calls to read_timer_{start,end}_of_tick_handler()
to mark the start and end of ISR which will be used to display
the time spent in ISR with benchmarking tests.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add a k_timeout_t type, and use it everywhere that kernel API
functions were accepting a millisecond timeout argument. Instead of
forcing milliseconds everywhere (which are often not integrally
representable as system ticks), do the conversion to ticks at the
point where the timeout is created. This avoids an extra unit
conversion in some application code, and allows us to express the
timeout in units other than milliseconds to achieve greater precision.
The existing K_MSEC() et. al. macros now return initializers for a
k_timeout_t.
The K_NO_WAIT and K_FOREVER constants have now become k_timeout_t
values, which means they cannot be operated on as integers.
Applications which have their own APIs that need to inspect these
vs. user-provided timeouts can now use a K_TIMEOUT_EQ() predicate to
test for equality.
Timer drivers, which receive an integer tick count in ther
z_clock_set_timeout() functions, now use the integer-valued
K_TICKS_FOREVER constant instead of K_FOREVER.
For the initial release, to preserve source compatibility, a
CONFIG_LEGACY_TIMEOUT_API kconfig is provided. When true, the
k_timeout_t will remain a compatible 32 bit value that will work with
any legacy Zephyr application.
Some subsystems present timeout (or timeout-like) values to their own
users as APIs that would re-use the kernel's own constants and
conventions. These will require some minor design work to adapt to
the new scheme (in most cases just using k_timeout_t directly in their
own API), and they have not been changed in this patch, instead
selecting CONFIG_LEGACY_TIMEOUT_API via kconfig. These subsystems
include: CAN Bus, the Microbit display driver, I2S, LoRa modem
drivers, the UART Async API, Video hardware drivers, the console
subsystem, and the network buffer abstraction.
k_sleep() now takes a k_timeout_t argument, with a k_msleep() variant
provided that works identically to the original API.
Most of the changes here are just type/configuration management and
documentation, but there are logic changes in mempool, where a loop
that used a timeout numerically has been reworked using a new
z_timeout_end_calc() predicate. Also in queue.c, a (when POLL was
enabled) a similar loop was needlessly used to try to retry the
k_poll() call after a spurious failure. But k_poll() does not fail
spuriously, so the loop was removed.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Replace all occurences of BUILD_ASSERT_MSG() with BUILD_ASSERT()
as a result of merging BUILD_ASSERT() and BUILD_ASSERT_MSG().
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
Convert older DT_INST_ macro use in litex drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in atmel sam0 drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in microchip drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in cc13xx_cc26xx drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The DSP wall clock timer on some Intel SoC is a timer driven
directly by external oscillator and is external to the CPU
core(s). It is not as fast as the internal core clock, but
provides a common and synchronized counter for all CPU cores
(which is useful for SMP).
This uses the RISCV timer as base as it is using 64-bit
counter.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit reworks the Xilinx TTC timer driver to use the "match" mode
instead of the "interval" mode which counts up to the specified value
and resets to zero.
Using the "match" mode ensures that the timer keeps counting even after
an interrupt is triggered, and facilitates the tickless mode support
implementation.
This also allows `z_timer_cycle_get_32` to return the correct cycle
count when interrupt is locked; thereby, fixing the k_busy_wait hang
issue.
Note that the TTC "match" mode emulation (and tickless timer operation)
is only stable when the QEMU icount mode is enabled.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This reverts commit 8739517107.
Pull Request #23437 was merged by mistake with an invalid manifest.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Replace all occurences of BUILD_ASSERT_MSG() with BUILD_ASSERT()
as a result of merging BUILD_ASSERT() and BUILD_ASSERT_MSG().
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
for smp target, there is a case where just one core is running, then:
* during init, the master core will run, others cores will halt/sleep
* use timer driver for single core
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Use DT_INST_* instead of the hard-coded macro from the HAL,
as DT_INST_* are preferred.
Fixes#17775
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When debugging on a long running platform, the MCU may get reset by
the debugger with an ndmreset toggle. Since there is no requirement
that this resets anything in particular on the platform, the CLINT
registers may not get reset. When this occurs with an mtime register
value that is larger than 32 bits the riscv machine timer will
continuously interrupt the system when the mtime register exceeds 32
bits in value. This is because the last_count value is used to update
the mtimecmp register, and its value is initialized to zero. Its
first update is with a 32-bit value, which loses information when the
mtime register exceeds 32 bits.
The proposed solution is to set the last_count value to the current
value in the mtime register when the timer is initialized. Since the
timer is fired at intervals that are less than 32 bits in value, the
next update of last_count will remain valid, and the system will
function as expected.
Signed-off-by: Jaron Kelleher <jkelleher@fb.com>
riscv64 CPUs can access full 64-bit memory-mapped register by a single
instruction, so we can directly access these registers.
Signed-off-by: Jim Shu <cwshu@andestech.com>
ARM cores may have a per-core architected timer, which provides per-cpu
timers, attached to a GIC to deliver its per-processor interrupts via
PPIs. This is the most common case supported by QEMU in the virt
platform.
This patch introduces support for this timer abstracting the way the
timer registers are actually accessed. This is needed because different
architectures (for example ARMv7-R vs ARMv8-A) use different registers
and even the same architecture (ARMv8-A) can actually use different
timers (ELx physical timers vs ELx virtual timers).
So we introduce the common driver here but the actual SoC / architecture
/ board must provide the three helpers (arm_arch_timer_set_compare(),
arm_arch_timer_toggle(), arm_arch_timer_count()) using an header file
imported through the arch/cpu.h header file.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The CONFIG_ prefixes were missing on these.
Found with a work-in-progress scripts/kconfig/lint.py check.
This symbol is defined in kernel/Kconfig.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The RTC peripheral found in the SAMD5x/SAME5x MCUs is very
simmilar to the one found in existing sam0 devices with only
a few changes to register names and the clock source selection.
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
Before introducing the code for ARM64 (AArch64) we need to relocate the
current ARM code to a new AArch32 sub-directory. For now we can assume
that no code is shared between ARM and ARM64.
There are no functional changes. The code is moved to the new location
and the file paths are fixed to reflect this change.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Low frequency and high frequency clocks had separate devices
while they are actually handled by single peripheral with single
interrupt. The split was done probably because opaque subsys
argument in the API was used for other purposes and there was
no way to pass the information which clock should be controlled.
Implementation changes some time ago and subsys parameter was
no longer used. It now can be used to indicate which clock should
be controlled.
Change become necessary when nrf5340 is taken into account where
there are more clocks and current approach would lead to create
multiple devices - mess.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Bool symbols implicitly default to 'n'.
A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.
Also replace some
config
prompt "foo"
bool/int
with the more common shorthand
config
bool/int "foo"
See the 'Style recommendations and shorthands' section in
https://docs.zephyrproject.org/latest/guides/kconfig/index.html.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
When setting a timeout measure the number of accumulated unannounced
ticks. If this value exceeds half the 24-bit cycle counter range
force an announcement so the unannounced cycles are incorporated into
the system tick counter.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Some early tickless drivers had a common pattern where they would
compute a tick maximum for the request (i.e. the maximum the hardware
counter can handle) but apply it only on the input tick value and not
on the adjusted final value, opening up the overflow condition it was
supposed to have prevented.
Fixes#20939 (Strictly it fixes the specific pattern that was
discovered in that bug. It's not impossible that other drivers with
alternative implementations have a similar issue, though they look OK
to me via a quick audit).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Similar to what we do in other timer drivers, the maximum ticks
supplied in z_clock_set_timeout(..) needs to be MAX_TICKS at
maximum, when K_FOREVER is supplied as argument to the function.
In addition to that, the value we load onto the SysTick LOAD
register shall be truncated to MAX_CYCLES. This is required
to prevent loading a trash value to LOAD register, as only
the lowest 24 bits may be safely written.
Finally, we move the enforcement of the minimum delay to be
programmed on LOAD (i.e. MIN_DELAY) at the end step of the
calculation of the cycles-to-be-programmed. This prevents
from misscalculating the delay, as any required adjustment
is applied at the end, after the delay is rounded up to
the next tick boundary.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When setting a timeout measure the number of accumulated unannounced
ticks. If this value exceeds half the 32-bit cycle counter range
force an announcement so the unannounced cycles are incorporated into
the system tick counter.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The commit fixes the update of the absolute counter of HW cycles
in the SysTick ISR for TICKLESS mode.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The previous solution depended on a magic number and was inefficient
(entered the second-wrap conditional even when a second wrap hadn't
been observed). Replace with an algorithm that is deterministic.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add detailed documentation for the internal 'elapsed()'
function, as well as for the local counter variables used
in the SysTick driver.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Unsupported bits of the Current Value Register
are read as zero, so we remove the redundant
ANDing with the max supported counter value.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The original code assumed that limiting the tick count to the maximum
cycle value representable without wrapping would guarantee that adding
the resulting cycle offset to last_count would not lap the counter.
This is not true when elapsed time, which is also added to the cycle
offset, exceeds one tick. Cap the maximum offset at the number of
cycles corresponding to the maximum number of ticks without wrapping.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
* fix the smp timer dirver bugs found in debug and test.
for smp case, GFRC is used as clock source, and local
internal timer is used to trigger time event.
* because 64-bits gfrc is used, so idle can be igored as no kernel
tick will be missed
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Mark the old time conversion APIs deprecated, leave compatibility
macros in place, and replace all usage with the new API.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Promote the private z_arch_* namespace, which specifies
the interface between the core kernel and the
architecture code, to a new top-level namespace named
arch_*.
This allows our documentation generation to create
online documentation for this set of interfaces,
and this set of interfaces is worth treating in a
more formal way anyway.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit refactors kernel and arch headers to establish a boundary
between private and public interface headers.
The refactoring strategy used in this commit is detailed in the issue
This commit introduces the following major changes:
1. Establish a clear boundary between private and public headers by
removing "kernel/include" and "arch/*/include" from the global
include paths. Ideally, only kernel/ and arch/*/ source files should
reference the headers in these directories. If these headers must be
used by a component, these include paths shall be manually added to
the CMakeLists.txt file of the component. This is intended to
discourage applications from including private kernel and arch
headers either knowingly and unknowingly.
- kernel/include/ (PRIVATE)
This directory contains the private headers that provide private
kernel definitions which should not be visible outside the kernel
and arch source code. All public kernel definitions must be added
to an appropriate header located under include/.
- arch/*/include/ (PRIVATE)
This directory contains the private headers that provide private
architecture-specific definitions which should not be visible
outside the arch and kernel source code. All public architecture-
specific definitions must be added to an appropriate header located
under include/arch/*/.
- include/ AND include/sys/ (PUBLIC)
This directory contains the public headers that provide public
kernel definitions which can be referenced by both kernel and
application code.
- include/arch/*/ (PUBLIC)
This directory contains the public headers that provide public
architecture-specific definitions which can be referenced by both
kernel and application code.
2. Split arch_interface.h into "kernel-to-arch interface" and "public
arch interface" divisions.
- kernel/include/kernel_arch_interface.h
* provides private "kernel-to-arch interface" definition.
* includes arch/*/include/kernel_arch_func.h to ensure that the
interface function implementations are always available.
* includes sys/arch_interface.h so that public arch interface
definitions are automatically included when including this file.
- arch/*/include/kernel_arch_func.h
* provides architecture-specific "kernel-to-arch interface"
implementation.
* only the functions that will be used in kernel and arch source
files are defined here.
- include/sys/arch_interface.h
* provides "public arch interface" definition.
* includes include/arch/arch_inlines.h to ensure that the
architecture-specific public inline interface function
implementations are always available.
- include/arch/arch_inlines.h
* includes architecture-specific arch_inlines.h in
include/arch/*/arch_inline.h.
- include/arch/*/arch_inline.h
* provides architecture-specific "public arch interface" inline
function implementation.
* supersedes include/sys/arch_inline.h.
3. Refactor kernel and the existing architecture implementations.
- Remove circular dependency of kernel and arch headers. The
following general rules should be observed:
* Never include any private headers from public headers
* Never include kernel_internal.h in kernel_arch_data.h
* Always include kernel_arch_data.h from kernel_arch_func.h
* Never include kernel.h from kernel_struct.h either directly or
indirectly. Only add the kernel structures that must be referenced
from public arch headers in this file.
- Relocate syscall_handler.h to include/ so it can be used in the
public code. This is necessary because many user-mode public codes
reference the functions defined in this header.
- Relocate kernel_arch_thread.h to include/arch/*/thread.h. This is
necessary to provide architecture-specific thread definition for
'struct k_thread' in kernel.h.
- Remove any private header dependencies from public headers using
the following methods:
* If dependency is not required, simply omit
* If dependency is required,
- Relocate a portion of the required dependencies from the
private header to an appropriate public header OR
- Relocate the required private header to make it public.
This commit supersedes #20047, addresses #19666, and fixes#3056.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Use this short header style in all Kconfig files:
# <description>
# <copyright>
# <license>
...
Also change all <description>s from
# Kconfig[.extension] - Foo-related options
to just
# Foo-related options
It's clear enough that it's about Kconfig.
The <description> cleanup was done with this command, along with some
manual cleanup (big letter at the start, etc.)
git ls-files '*Kconfig*' | \
xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Clean up space errors and use a consistent style throughout the Kconfig
files. This makes reading the Kconfig files more distraction-free, helps
with grepping, and encourages the same style getting copied around
everywhere (meaning another pass hopefully won't be needed).
Go for the most common style:
- Indent properties with a single tab, including for choices.
Properties on choices work exactly the same syntactically as
properties on symbols, so not sure how the no-indentation thing
happened.
- Indent help texts with a tab followed by two spaces
- Put a space between 'config' and the symbol name, not a tab. This
also helps when grepping for definitions.
- Do '# A comment' instead of '#A comment'
I tweaked Kconfiglib a bit to find most of the stuff.
Some help texts were reflowed to 79 columns with 'gq' in Vim as well,
though not all, because I was afraid I'd accidentally mess up
formatting.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
There are two set of code supporting x86_64: x86_64 using x32 ABI,
and x86 long mode, and this consolidates both into one x86_64
architecture and SoC supporting truly 64-bit mode.
() Removes the x86_64:x32 architecture and SoC, and replaces
them with the existing x86 long mode arch and SoC.
() Replace qemu_x86_64 with qemu_x86_long as qemu_x86_64.
() Updates samples and tests to remove reference to
qemu_x86_long.
() Renames CONFIG_X86_LONGMODE to CONFIG_X86_64.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Removed workarounds in systick driver as they prevent normal usage in
TICKLESS systems. Driver still behaved like an interrupt based ticker.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Defining a symbol with 'menuconfig' just tells the menuconfig to display
any dependent symbols that immediately follow it in a separate menu.
'menuconfig' has no effect on symbol values.
Making a symbol that doesn't have any dependent symbols after it a
'menuconfig' should be avoided, because then you end up with an empty
menu, which is shown as e.g.
[*] Enable foo ---
This is how it would be shown if there were children but they all
happened to be invisible as well.
With a regular 'config', it turns into
[*] Enable foo
Change all pointless 'menuconfig's to 'config's.
See the section on 'menuconfig' on the Kconfig - Tips and Best Practices
page as well.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit switches from using device tree automatically
generated address-based defines to the instance id-based ones.
Without this change it is not be possible to re-use the driver
on boards where the device is located at different location
than 0xe0002800.
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This patch re-namespaces global variables and functions
that are used only within the arch/arm/ code to be
prefixed with z_arm_.
Some instances of CamelCase have been corrected.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fix an inline comment in nrf_rtc_timer.c correcting the
path to the mentioned test.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Global variables related to timing information have been
renamed to be prefixed with z_arch, with naming arranged
in increasing order of specificity.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
At least twice (to be fair: twice among thousands of test runs), I've
seen this device return "backwards" times in SMP, where the counter
value read from one CPU is behind the saved value already seen on the
other. On hardware this should obviously never happen, HPET is a
single global device.
Add a simple workaround on QEMU targets so the math doesn't blow up.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Header files of nrfx HALs are not supposed to be included directly
but only with their names prepended with the hal/ directory (so that
an inclusion of an nrfx HAL header clearly differs from an inclusion
of an nrfx driver header).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add RTC timer driver for CC13X2/CC26X2, and use it instead of systick
as system clock. It is necessary to use this timer for power
management support, so that the system can exit from deep sleep upon
expiry of timeouts.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
This driver was still using CONFIG_* values to determine its address,
IRQ, etc. Add a binding for an "intel,hpet" device and migrate this
driver to devicetree.
Fixes: #18657
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
We re-wrote the xtensa arch code, but never got around
to purging the old implementation.
Removed those boards which hadn't been moved to the new
arch code. These were all xt-sim simulator targets and not
real hardware.
Fixes: #18138
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
MEC1501 RTOS timer internal counter is on the 32KHz clock domain.
The register interface is on the AHB clock. When the timer is started
hardware synchronizes to the next 32KHz clock edge resulting is a
variable delay moving the value in the preload register into the
count register. The maximum delay is one 32KHz clock period (30.5 us).
We work-around this delay by checking if the timer has been started
and not using the count value which is still 0. Instead we state zero
counts have elapsed.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The variable enabling entry to the zero latency interrupt compensation
loop was named generically, and its logic inverted, making the code
difficult to understand. Change the name and initial value to more
clearly indicate its role.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
* it's based on ARC SecureShield
* add basic secure service in arch/arc/core/secureshield
* necesssary changes in arch level
* thread switch
* irq/exception handling
* initialization
* add secure time support
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
* use global free running counter as global wall clock (clock source)
* use arc internal timer 0 as local time event (clock event)
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Update the logic in a corner case, when the target comparator value is
one cycle ahead of the counter value.
Experiments have shown, that `set_comparator(cyc + 1);` might be not
enough in that case, and we still may (rarely) miss the interrupt.
This could happen when the counter incremented its value after the `dt`
variable was set. As we should set the comparator value two cycles
ahead to be on the safe side, increment the target comparator value
by 2 instead of 1.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
On some SoCs the frequency of the system clock is obtained at run time
as the exact configuration of the hardware is not known at compile time.
On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define
directly introduces timing errors.
This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call
to inline function sys_clock_hw_cycles_per_sec() which always returns
correct frequency of the system clock.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The native_posix timer driver was still using the
legacy timer API.
Replace it with a new version, which is aligned with
the new kernel<->system timer driver API,
and which has TICKLESS_CAPABLE support
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
When the tick rate was less than MIN_DELAY, bumping a "too soon"
expiration by just one tick may not be enough and we could
theoretically miss the counter.
Instead, eliminate the MIN_DELAY computation and write to the spec:
NRF guarantees that the RTC will generate an interrupt for a
comparator value two cycles in the future. And further, we can test
at the set point to see if we "just missed" the interrupt (i.e. zero
cycles delay) and flag a synchronous interrupt. So we only need to
miss a requested interrupt now for the special case of exactly one
cycle in the future, and then we're only late by one cycle. That's
optimal.
Also fixes an off-by-one in the next cycle computation. By API
convention, an ticks argument of one or less means "at the next tick"
and not "right now". So we need to add one to the target cycle to
avoid incorrectly triggering a synchronous interrupt. This was a
non-issue when a tick is longer than a hardware cycle but is needed
now.
Also handles the edge case with zero latency interrupts (which are
unmaskable) which might mess up timing. This was always a problem,
but we're more sensitive now and it's comparatively more likely to
occur.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The MVIC is no longer supported, and only the APIC-based interrupt
subsystem remains. Thus this layer of indirection is unnecessary.
This also corrects an oversight left over from the Jailhouse x2APIC
implementation affecting EOI delivery for direct ISRs only.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This is an oddball API. It's untested. In fact testing its proper
behavior requires very elaborate automation (you need a device outside
the Zephyr hardware to measure real world time, and a mechanism for
getting the device into and out of idle without using the timer
driver). And this makes for needless difficulty managing code
coverage metrics.
It was always just a hint anyway. Mark the old API deprecated and
replace it with a kconfig tunable. The effect of that is just to
change the timeout value passed to the timer driver, where we can
manage code coverage metrics more easily (only one driver cares to
actually support this feature anyway).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move clock_control.h to drivers/clock_control.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move power.h to power/power.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Fix path for system_timer.h and loapic.h, we moved it to
include/drivers/timer/ and include/drivers/interrupt_controller/
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The existing local APIC timer driver (loapic_timer.c) has bitrotted
and doesn't support TICKLESS_KERNEL, which is the preferred mode of
operation. This patch introduces a completely new driver, called
the APIC timer driver - the name is changed to allow the drivers to
continue to coexist in the short term, and also because "APIC timer"
isn't ambiguous (the I/O APICs do not have timers).
This driver makes no attempt to work with the MVIC timer as the
previous version did, because MVIC support is deprecated.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Move internal and architecture specific headers from include/drivers to
subfolder for timer:
include/drivers/timer
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Quark D2000 is the only x86 with an MVIC, and since support for
it has been dropped, the interrupt controller is orphaned. Removed.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The defines related to IRQ priority don't exist and aren't used. So
just pass 0 to IRQ_CONNECT for the priority field.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The defines should have had a _0 on them, now that we generate the
proper defines, fixup the cases that used that old scheme.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Found a few annoying typos and figured I better run script and
fix anything it can find, here are the results...
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change code from using now deprecated DT_<COMPAT>_<INSTANCE>_<PROP>
defines to using DT_INST_<INSTANCE>_<COMPAT>_<PROP>.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
More clearly differentiate MVIC vs. APIC timer code, and use new APIC
accessors in include/drivers/loapic.h. Remove extraneous comments, and
other light cleanup work.
This driver is in need of a serious overhaul -- despite appearing to
have support for TICKLESS_KERNEL and DEVICE_POWER_MANAGEMENT, bitrot
has taken its toll and the driver will not build with these enabled.
These should be removed or made to work... but not in this patch.
Old x2APIC-related accessors in kernel_arch_func.h are eliminated.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Simple renaming and Kconfig reorganization. Choice of local APIC
access method isn't specific to the Jailhouse hypervisor.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The litex_timer driver used hard coded tick rate (set to 100 ticks
per second). This commit replaces the fixed value with a call to
system function which takes under account system configuration.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
Add LiteX timer driver with bindings for this device.
Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
We shall not enable by default a system timer in ARM
platforms, namely the SysTick, the Nordic, or the SAM0
RTC timer, simply by assessing the hardware capabilities
(e.g. by conditioning on CPU_CORTEX_M_HAS_SYSTICK).
Instead, now, all ARM platforms needs to explicitly set
their system timer module. Note that this has already
been the case for ca 80% of the ARM platforms.
This clean-up allows us to decouple HW capabilities from
system configuration (for example, Nordic platforms may
enable option CPU_CORTEX_M_HAS_SYSTICK, and still use
the platform-specific RTC timer for system timing).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit renames the symbol CPU_HAS_SYSTICK to
CPU_CORTEX_M_HAS_SYSTICK, to look similar to all
other CPU_CORTEX_M_HAS_ options, and moves the
K-config symbol definition from arm/core/Kconfig to
arm/core/cortex_m/Kconfig.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Enabling the RTC event is intended to support peripheral-to-peripheral
interconnects, so introduces a request for HFCLK and PCLK16M when the
event is triggered. This specific event is never used with PPI so
enabling events apparently does nothing but increase power consumption.
Closes#15513
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Clearing the pending IRQs when resetting the timeout fixes the
forward time drifting, but the change needs more investigation
until we are sure this won't break kernel time management.
Reverting the change to get 1.14 release out.
This reverts commit 2895da02a4.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In the unlucky scenario of a SysTick event (wrap) occurring
while we re-program the last_load value, the SysTick ISR
will run immediately after we unlock interrupts. In that
case the timeout we have just configured will expire
instantaneously, leading to operations being executed
much earlier than expected. Avoid this by clearing possibly
pending SysTick exceptions (writing 1 to ICSR.PENDSTCLR).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When the counter reaches zero, it reloads the value in
SYST_RVR on the next clock edge. This means that if the
LOAD value is N, the interrupt ("tick") is triggered
every N+1 cycles. Therefore, when we operate in tickless
mode, and we want to schedule the next timeout, we need
to configure the LOAD value with last_load - 1, in order
to get an event in last_load cycles.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When the counter reaches zero, it reloads the value in
SYST_RVR on the next clock edge. This means that if the
LOAD value is N, the interrupt ("tick") is triggered
every N+1 cycles. Therefore, when we operate in non-
tickless mode, we need to configure the LOAD value
with CYC_PER_TICK - 1, in order to get an event
every CYC_PER_TICK cycles.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The SysTick logic looked logically sound, but it was allowing us to
set a LOAD value as low as 512 cycles. On other platforms, that
minimum future interrupt delay is there to protect the "read, compute,
write, unmask" cycle that sets the new interrupt from trying to set
one sooner than it can handle.
But with SysTick, that value then becomes the value of the LOAD
register, which is effectively the frequency with which timer
interrupts arrive. This has two side effects:
1. It opens up the possibility that future code that masks interrupts
longer than 512 cycles will miss more than one overflow, slipping
the clock backward as viewed by z_clock_announce().
2. The original code only understood one overflow cycle, so in the
event we do set one of these very near timeouts and then mask
interrupts, we'll only add at most one overflow to the "elapsed()"
time, slipping the CURRENT time backward (actually turning it into
a non-monotonic sawtooth which would slip every LOAD cycle) and
thus messing up future scheduled interrupts, slipping those forward
relative to what the ISR was counting.
This patch simplifies the logic for reading SysTick VAL/CTRL (the loop
wasn't needed), handles the case where we see more than one overflow,
and increases the MIN_DELAY cycles from 512 to 1/16th of a tick.
Fixes#15216
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename reserved function names in drivers/ subdirectory. Update
function macros concatenatenating function names with '##'. As
there is a conflict between the existing gpio_sch_manage_callback()
and _gpio_sch_manage_callback() names, leave the latter unmodified.
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Per #13610, recent changes to this driver seem to have introduced
unexpected latency regressions. This patch effectively reverts these
patches which changed the meat of the driver:
ac36886e62 drivers: nrf: timer: add inline qualifier where
inlining is intended
084363a0dc drivers: timer: nrf: refactor for speed and correctness
71882ff8c4 drivers: timer: nrf: drop unnecessary counter mask
4b24e88fa4 drivers: timer: nrf: use irq_lock instead of spinlock
While backporting these seemingly unrelated hygiene patches:
7cbdb6c5c0 drivers/timer: Restore non-tickless tick count behavior
d30c9aeafd drivers: nrf_power_clock: Migrate to DTS.
75f77db432 include: misc: util.h: Rename min/max to MIN/MAX
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The existing device_set_power_state() API works only in synchronous
mode and this is not desirable for devices(ex: Gyro) which take
longer time (few 100 mSec) to suspend/resume.
To support async mode, a new callback argument is added to the API.
The device drivers can asynchronously suspend/resume and call the
callback function upon completion of the async request.
This commit adds the missing callback parameter to all the drivers
to make it compliant with the new API.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
This is intended to initialize CPU-local timer devices, but HPET is
global so we have nothing to do.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Redefining the config will not let another (out-of-source) driver be
chosen instead of the default. The driver is practically forced by the
soc settings. This commit moves default settings from soc/arm/nordic_nrf
into the drivers themselves.
Signed-off-by: Thomas Stenersen <thomas.stenersen@nordicsemi.no>
Update reserved function names starting with one underscore, replacing
them as follows:
'_k_' with 'z_'
'_K_' with 'Z_'
'_handler_' with 'z_handl_'
'_Cstart' with 'z_cstart'
'_Swap' with 'z_swap'
This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.
Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.
Various generator scripts have also been updated as well as perf,
linker and usb files. These are
drivers/serial/uart_handlers.c
include/linker/kobject-text.ld
kernel/include/syscall_handler.h
scripts/gen_kobject_list.py
scripts/gen_syscall_header.py
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Converts the rv32m1 timer driver to use 'DT_' prefixed defines instead
of deprecated non-prefixed defines.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The newer series of timer drivers will compare counters vs. the last
tick boundary to compute a number of ticks to announce to the kernel.
In the case of CONFIG_TICKLESS=n, this actually represents a change of
behavior from our old scheme where "ticks" always reflected the number
of interrupts received.
The distinction only matters when an interrupt is delayed more than a
full tick, of course. But that actually makes a difference to some
timekeeping code. Restore the old behavior.
This also has the benefit of further reducing code size when !TICKLESS
and improving performance of the ISR by removing the division
(remember Cortex M0 has no hardware divide!).
Fixes#12409
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There are issues using lowercase min and max macros when compiling a C++
application with a third-party toolchain such as GNU ARM Embedded when
using some STL headers i.e. <chrono>.
This is because there are actual C++ functions called min and max
defined in some of the STL headers and these macros interfere with them.
By changing the macros to UPPERCASE, which is consistent with almost all
other pre-processor macros this naming conflict is avoided.
All files that use these macros have been updated.
Signed-off-by: Carlos Stuart <carlosstuart1970@gmail.com>
nrf_rtc_timer was selecting counter RTC1 instance even though it
is not using counter API at all.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The system timer uses RTC1, but does not implement the counter API with
it. Instead of auto-enabling the counter API on the system timer make
the two conflict until/unless both APIs are supported by the peripheral.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The selection of the Cortex M systick driver to be used
as a system clock driver is controlled by
CONFIG_CORTEX_M_SYSTICK.
To replace it by another driver CONFIG_CORTEX_M_SYSTICK
must be set to 'n'. Unfortunately this also controls
the interrupt vector for the systick interrupt. It is
now routed to __reserved. More bad the interrupt vector
can not be set by IRQ_CONNECT as it is one of the hard
coded interrupts in the interrupt table.
Route the hard coded systick interrupt to z_clock_isr
and make z_clock_isr a weak symbol that can be overwritten
by an alternative systick system clock driver.
Signed-off-by: Bobby Noelte <b0661n0e17e@gmail.com>
This board is unmaintained and unsupported. It is not known to work and
has lots of conditional code across the tree that makes code
unmaintainable.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
* MIN_DELAY: 1024 -> 512
* optimzie some code sequence
* fix a bug in setting the new timer limit value
* case: before set limit register with new value,
if counter rolls back to 0, the limit value should be
adjusted.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
The smp_timer_init() was removed during timer re-write.
This results in undefined references error during compilation
when CONFIG_SMP=y. So add it back so we can compile for SMP.
The logic is updated from the previous version to the latest
in the driver.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add sam0_rtc_driver that implements system timer API on top of the RTC
and can be used as a replacement for the default systick timer.
Signed-off-by: Martin Benda <martin.benda@omsquare.com>
Add a level 2 interrupt controller for the RV32M1 SoC. This uses the
INTMUX peripheral.
As a first customer, convert the timer driver over to using this,
adding nodes for the LPTMR peripherals. This lets users select the
timer instance they want to use, and what intmux channel they want to
route its interrupt to, using DT overlays.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Mike Scott <mike@foundries.io>
The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V
32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two
cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC
enablement for the RISC-V cores:
- basic dtsi, to be extended as additional drivers are added
- SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY
- system timer driver for RI5CY, based on LPTMR0 peripheral
The timer driver will be generalized a bit soon once proper
multi-level interrupt support is available.
Emphasis is on supporting the RI5CY core as the more capable of the
two; the ZERO-RISCY SoC definitions are a good starting point, but
additional work setting up a dtsi and initial drivers is needed to
support that core.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Michael Scott <mike@foundries.io>
Not necessary with gcc, and Zephyr is inconsistent about using the
qualifier, but making the intent explicit is a good thing.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The existing implementation of z_clock_set_timeout() calculates the
compare value based on a complex series of operations including an
unconditional integer division and multiplication intended to ensure the
compare value is aligned to a tick boundary. On the nRF51 this division
requires a call to an outline function with a data-dependent execution
time.
In the common case where the timeout is set less than one tick past the
last observed tick the devision can be elided, as can several extra
operations intended to deal with fractional ticks.
The code also failed to account for a ticks-per-cycle that violated the
minimum delay required to guarantee a compare value would result in a
match without wrapping. The minimum delay was also unreasonably long
(about 1 ms). Reduce it to a more reasonable value to allow for a
higher ticks-per-second, and diagnose attempts to set the tick frequency
above the supported maximum (8192 Hz).
Finally, move the parts of the compare calculation that are not
dependent on the live counter value out of the locked region.
Prior to this change the observed time between the irq_lock() and
irq_unlock() in z_clock_set_timeout() on the nRF51 ranged between 5 us
and 8 us.
With the revised algorithm the observed lock duration is between 2.16 us
(1024 Hz) and 2.88 us (100 Hz) in the common case that the compare is
set within the current tick. If the compare is set late the duration
will be higher, but no greater than the previous implementation.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The RTC COUNTER register doesn't care that it receives a value larger
than it can hold; it'll discard the bits internally. No need to spend
cycles doing it manually.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
spinlock gains us nothing on an architecture that doesn't support SMP.
Use the standard irq_lock() API so when we search for conditions that
may decrease ISR responsiveness we can find them.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Cleanup dependencies in Kconfig and convert some top-level options to
menuconfig. guard all dependent options with if instead of using
'depends on' for readibility.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Minor adjustments are done to the nRF clock_control and rtc_timer
drivers to make them usable on nRF9160 as well.
The arm_irq_vector_table test code is modified only because it uses
the function that has been renamed in the nrf_rtc_timer driver.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit renames the nrf5_clock_control.h and
nrf5_clock_control.c files to nrf_clock_control.h and
nrf_clock_control.c, respectively, as they are used
in nRF9160 builds, as well.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit renames the CLOCK_CONTROL_NRF5 Kconfig symbol to
CLOCK_CONTROL_NRF. The change is required to aleviates confusion
when selecting the symbol in nRF9160 SOC definition.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When tickless was disabled, this inverted test would never fire the
first interrupt and the timer would be silent. Just remove it.
There's no harm in unconditionally enabling a single timer interrupt
at boot.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().
The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.
Limitations:
+ Right now the SDK lacks an x86_64 toolchain. The build will fall
back to a host toolchain if it finds no cross compiler defined,
which is tested to work on gcc 8.2.1 right now.
+ No x87/SSE/AVX usage is allowed. This is a stronger limitation than
other architectures where the instructions work from one thread even
if the context switch code doesn't support it. We are passing
-no-sse to prevent gcc from automatically generating SSE
instructions for non-floating-point purposes, which has the side
effect of changing the ABI. Future work to handle the FPU registers
will need to be combined with an "application" ABI distinct from the
kernel one (or just to require USERSPACE).
+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
of all memory. No MMU/USERSPACE support yet.
+ We are building with -mno-red-zone for stack size reasons, but this
is a valuable optimization. Enabling it requires automatic stack
switching, which requires a TSS, which means it has to happen after
MMU support.
+ The OS runs in 64 bit mode, but for compatibility reasons is
compiled to the 32 bit "X32" ABI. So while the full 64 bit
registers and instruction set are available, C pointers are 32 bits
long and Zephyr is constrained to run in the bottom 4G of memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The HPET default is to deliver events on the same INTIn as the legacy
PIT IRQ, and in fact our code requires that because it uses the
"legacy routing" option. So this isn't really a configurable and has
to be set correctly. Do it right in the kconfig default instead of
forcing boards to set it.
(No, I have no idea where "20" came from either.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This patch fixes a bug in System timer driver where
the sys_clock_disable() function was enabling the
timer instead of disabling it.
Change-Id: I4a667d30d43d1f84094d074241ee18d7bb2b2565
Signed-off-by: David Vincze <david.vincze@arm.com>
Two subtractions failed to account for the possibility that a calculated
time exceeded the counter resolution, allowing a comparison to
improperly indicate that a minimum delay was satisfied.
Use the subtraction helper to avoid the problem.
(The subtraction in z_clock_set_timeout was the cause of issue #11694;
the one in rtc1_nrf5_isr was replaced based on inspection rather than
testing.)
Closes#11694
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
If we just had the kernel's implementation, we could
just move this to lib/, but possible arch-specific
implementations dictate that we just make this a
syscall.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We still have one platform using (for now) the pre-asm2 integration
where the timer interrupt was handled via custom assembly. It calls a
function named "_timer_int_handler" always, not the one we register
with IRQ_CONNECT.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Rewritten Xtensa CCOUNT driver along the lines of all the other new
drivers. The new API permits much smaller code.
Notably: The Xtensa counter is a 32 bit up-counter with a comparator
register. It's in some sense the archetype of this kind of timer as
it's the simplest of the bunch (everything else has quirks: NRF is
very slow and 24 bit, HPET has a runtime frequency detection, RISC-V
is 64 bit...). I should have written this one first.
Note also that this includes a blacklist of the xtensa architecture on
the tests/driver/ipm test. I'm getting spurious failures there where
a k_sem_take() call with a non-zero timeout is being made out of the
console output code in interrupt context. This seems to have nothing
to do with the timer; I suspect it's because the old timer drivers
would (incorrectly!) call z_clock_announce() in non-interrupt context
in some contexts (e.g. "expiring really soon"). Apparently this test
(or something in the IPM or Xtensa console code) was somehow relying
on that on Xtensa. But IPM is a Quark thing and there's no particular
reason to run this test there.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Rewritten driver along the lines of all the other new drivers,
implementing the new timer API. Structurally, the machine timer is an
up-counter with comparator, so it works broadly the same way HPET and
NRF do. The quirk here is that it's a 64 bit counter, which needs a
little more care.
Unlike the other timer reworks, this driver has grown by a few lines
as it used to be very simple. But in exchange, we get full tickless
support on the platform.
Fixes#10609 in the process (the 64 bit timer registers are unlatched
for sub-word transfers, so you have to use careful ordering).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Reworked using the older hardware interface code, but with an
implementation of the new API only. Much smaller & simpler.
As yet, tested (manually) only on a nrf52_pca10056 board.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Rewritten along the lines of ARM SysTick. Implements only the new,
simplified API. MUCH smaller. Works with tickless pervasively. No
loss of functionality.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Many drivers won't need to implement z_clock_idle_exit() or
sys_clock_disable(). Make those weak stubs too.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a TICKLESS_CAPABLE kconfig variable which is used by the kernel to
select tickless mode's default automatically on drivers that support
it (rather than having to set the default per-board). Select it from
the ARM SysTick and Intel HPET drivers.
Also remove the old qemu_cortex_m3 default settings which this
replaces.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Qemu doesn't like tickless. By default[1] it tries to be realtime as
vied by the host CPU -- presenting read values from hardware cycle
counters and interrupt timings at the appropriate real world clock
times according to whatever the simulated counter frequency is. But
when the host system is loaded, there is always the problem that the
qemu process might not see physical CPU time for large chunks of time
(i.e. a host OS scheduling quantum -- generally about the same size as
guest ticks!) leading to lost cycles.
When those timer interrupts are delivered by the emulated hardware at
fixed frequencies without software intervention, that's not so bad:
the work the guest has to do after the interrupt generally happens
synchronously (because the qemu process has just started running) and
nothing notices the dropout.
But with tickless, the interrupts need to be explicitly programmed by
guest software! That means the driver needs to be sure it's going to
get some real CPU time within some small fraction of a Zephyr tick of
the right time, otherwise the computations get wonky.
The end result is that qemu tends to work with tickless well on an
unloaded/idle run, but not in situations (like sanitycheck) where it
needs to content with other processes for host CPU.
So, add a flag that drivers can use to "fake" tickless behavior when
run under qemu (only), and enable it (only!) for the small handful of
tests that are having trouble.
[1] There is an -icount feature to implement proper cycle counting at
the expense of real-world-time correspondence. Maybe someday we might
get it to work for us.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Newer, and much smaller driver written to the new timer API. Supports
all the features the old one did (including shutting off the clock
when clock_always_on is disabled), should be faster in practice, and
should be significantly more accurate due to the "lost cycle" trick
applied in z_clock_set_timeout().
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Since CCOMPARE* registers have undefined values after reset,
set compare value first before enabling timer interrupt.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
I was pretty careful, but these snuck in. Most of them are due to
overbroad string replacements in comments. The pull request is very
large, and I'm too lazy to find exactly where to back-merge all of
these.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Now that the API has been fixed up, replace the existing timeout queue
with a much smaller version. The basic algorithm is unchanged:
timeouts are stored in a sorted dlist with each node nolding a delta
time from the previous node in the list; the announce call just walks
this list pulling off the heads as needed. Advantages:
* Properly spinlocked and SMP-aware. The earlier timer implementation
relied on only CPU 0 doing timeout work, and on an irq_lock() being
taken before entry (something that was violated in a few spots).
Now any CPU can wake up for an event (or all of them) and everything
works correctly.
* The *_thread_timeout() API is now expressible as a clean wrapping
(just one liners) around the lower-level interface based on function
pointer callbacks. As a result the timeout objects no longer need
to store backpointers to the thread and wait_q and have shrunk by
33%.
* MUCH smaller, to the tune of hundreds of lines of code removed.
* Future proof, in that all operations on the queue are now fronted by
just two entry points (_add_timeout() and z_clock_announce()) which
can easily be augmented with fancier data structures.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The current z_clock_uptime() call (recently renamed from
_get_elapsed_program_time) requires the driver to track a full 64 bit
uptime value in ticks, which is entirely separate from the one the
kernel is already keeping.
Don't do that. Just ask the drivers to track uptime since the last
call to z_clock_announce(), since that is going to map better to
built-in hardware capability.
Obviously existing drivers already have this feature, so they're
actually getting slightly larger in order to implement the new API in
terms of the old one. But future drivers will thank us.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Useful for tick-only drivers like Pulpino that don't support this.
Ideally we'd have a header-level interface definition for individual
timer drivers to eliminate the noop function call, but this is clean
for now (even the Pulpino hardware looks like it should support
timeouts just fine, so effort would be better spent there than on a
clean "ticked" interface).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The tickless driver had a bunch of "hairy" APIs which forced the timer
drivers to do needless low-level accounting for the benefit of the
kernel, all of which then proceeded to implement them via cut and
paste. Specifically the "program_time" calls forced the driver to
expose to the kernel exactly when the next interrupt was due and how
much time had elapsed, in a parallel API to the existing "what time is
it" and "announce a tick" interrupts that carry the same information.
Remove these from the kernel, replacing them with synthesized logic
written in terms of the simpler APIs.
In some cases there will be a performance impact due to the use of the
64 bit uptime call, but that will go away soon.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Rename timer driver API functions to be consistent. ADD DOCS TO THE
HEADER so implementations understand what the requirements are.
Remove some unused functions that don't need declarations here.
Also removes the per-platform #if's around the power control callback
in favor of a weak-linked noop function in the driver initialization
(adds a few bytes of code to default platforms -- we'll live, I
think).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The existing API had two almost identical functions: _set_time() and
_timer_idle_enter(). Both simply instruct the timer driver to set the
next timer interrupt expiration appropriately so that the call to
z_clock_announce() will be made at the requested number of ticks. On
most/all hardware, these should be implementable identically.
Unfortunately because they are specified differently, existing drivers
have implemented them in parallel.
Specify a new, unified, z_clock_set_timeout(). Document it clearly
for implementors. And provide a shim layer for legacy drivers that
will continue to use the old functions.
Note that this patch fixes an existing bug found by inspection: the
old call to _set_time() out of z_clock_announce() failed to test for
the "wait forever" case in the situation where clock_always_on is
true, meaning that a system that reached this point and then never set
another timeout would freeze its uptime clock incorrectly.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There were three separate "announce ticks" entry points exposed for
use by drivers. Unify them to just a single z_clock_announce()
function, making the "final" tick announcement the business of the
driver only, not the kernel.
Note the oddness with "_sys_idle_elapsed_ticks": this was a global
variable exposed by the kernel. But it was never actually used by the
kernel. It was updated and inspected only within the timer drivers,
and only so that it could be passed back to the kernel as the default
(actually hidden) argument to the announce function. Break this false
dependency by putting this variable into each timer driver
individually.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The system tick count is a 64 bit quantity that gets updated from
interrupt context, meaning that it's dangerously non-atomic and has to
be locked. The core kernel clock code did this right.
But the value was also exposed to the rest of the universe as a global
variable, and virtually nothing else was doing this correctly. Even
in the timer ISRs themselves, the interrupts may be themselves
preempted (most of our architectures support nested interrupts) by
code that wants to set timeouts and inspect system uptime.
Define a z_tick_{get,set}() API, eliminate the old variable, and make
sure everyone uses the right mechanism.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This was another "global variable" API. Give it function syntax too.
Also add a warning, because on nRF devices (at least) the cycle clock
runs in kHz and is too slow to give a precise answer here.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This just got turned into a function from a "variable" API, but
post-the-most-recent-patch it turns out to be degenerate anyway.
Everyone everywhere should always have been using the kconfig variable
directly, and it was only a weirdness in the tickless API that made it
confusing. Fix.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The existing API defined sys_clock_{hw_cycles,ticks}_per_sec as simple
"variables" to be shared, except that they were only real storage in
certain modes (the HPET driver, basically) and everywhere else they
were a build constant.
Properly, these should be an API defined by the timer driver (who
controls those rates) and consumed by the clock subsystem. So give
them function syntax as a stepping stone to get there.
Note that this also removes the deprecated variable
_sys_clock_us_per_tick rather than give it the same treatment.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Simplify the Kconfig dependency for the nrf timer driver.
CLOCK_CONTROL_NRF5 depends on the SOC_FAMILY_NRF already.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Add support for CONFIG_SYSTEM_CLOCK_DISABLE so applications
may be compiled with CONFIG_REBOOT.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
The code assumes that when the systick counter hits zero,
the timer interrupt will be taken before the loop can
read the LOAD/VAL registers, but this is not architecturally
guaranteed, and so the code can see a post-reload SysTick->VAL
and a pre-reload clock_accumulated_count, which causes it to
return an incorrectly small cycle count. By adding a ISB we
overcome this issue.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Move to more generic tracing hooks that can be implemented in different
ways and do not interfere with the kernel.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Define generic interface and hooks for tracing to replace
kernel_event_logger and existing tracing facilities with something more
common.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch provides support needed to get timing related
information from riscv32 based SOC.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
This patch provides support needed to get timing related
information from nios2 based SOC.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
This patch provides support needed to get timing related
information from xtensa based SOC.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
The benchmark application timing_info needs certain hooks to be
present in the kernel to get the accurate measurements. This
patch adds these hook at all the required locations.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
irq_lock returns an unsigned int, though, several places was using
signed int. This commit fix this behaviour.
In order to avoid this error happens again, a coccinelle script was
added and can be used to check violations.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Consistently use
config FOO
bool/int/hex/string "Prompt text"
instead of
config FOO
bool/int/hex/string
prompt "Prompt text"
(...and a bunch of other variations that e.g. swapped the order of the
type and the 'prompt', or put other properties between them).
The shorthand is fully equivalent to using 'prompt'. It saves lines and
avoids tricking people into thinking there is some semantic difference.
Most of the grunt work was done by a modified version of
https://unix.stackexchange.com/questions/26284/how-can-i-use-sed-to-replace-a-multi-line-string/26290#26290, but some
of the rarer variations had to be converted manually.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit removes redundant reads of RTC_COUNTER register
propagating optimizations made in the k_cycle_get_32() function.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The previous implementation of _timer_cycle_get_32() (which is directly
mapped to k_cycle_get_32()) taken from 87 to 132 cycles. As result it
was too heavy for using it as source of time for logger.
This commit makes this function faster by removing redundant access
to the RTC register (each access consumed 28 CPU cycles) as well as
loop, which made this call non-deterministic.
After these changes the k_cycle_get_32() needs only 50-52 cycles
in to calculate 32-bit timestamp.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
A few function prototypes were missing in the native_posix
board and its drivers.
Let's add them.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Intel SDM Vol3 10.5.4.1 states that "A write to LVT Timer Register that
changes the timer mode disarms the local APIC timer".
This implies that LVT Timer register needs to be programmed before
Initial Count register, otherwise the LOAPIC timer could not be armed.
Signed-off-by: Zide Chen <zide.chen@intel.com>
On some architectures tick time cannot be expressed as integer
number of microseconds, introducing error in calculations using
sys_clock_us_per_tick variable.
This commit deprecates the sys_clock_us_per_tick variable and
replaces its usage by more precise calculations based on
sys_clock_hw_cycles_per_sec and sys_clock_ticks_per_sec.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
In case of tickless kernel, k_busy_wait() calls __enable_sys_clock()
which in turn calls _set_time() with maximum RTC counter programmable
value. This will set the expected_sys_ticks to maximum tick value even
though there is no explicit timeout is requested from the kernel or from
an application. In this scenario, if an app calls k_sleep() which in
turn calls _add_timeout() which will adjust timeout value as per the
elapsed program time which based on incorrectly set expected_sys_ticks.
To fix this issue, we should not set the expected_sys_ticks in case
of __enable_sys_clock() as it just requests to run the counter but
a timeout event request.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Bool symbols implicitly default to 'n'.
A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though, and is
inconsistent.
This will make the auto-generated Kconfig documentation have "No
defaults. Implicitly defaults to n." as well, which is clearer than
'default n if ...'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Uncovered by clang we have some functions being only used conditionally,
so gaurd them to make them only available when those conditions are met.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
To enable for easier testing, replace direct use of registers
from Nordic's nrfx MDK with accesses via its HAL inlined functions
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
The nrf_rtc_timer used own method to calculate number of timer cycles
per tick. As the result value was different than the one used by
the kernel, the reported time was incorrect.
This commit fixes the problem described above by using global
sys_clock_hw_cycles_per_tick instead of custom RTC_TICKS_PER_SYS_TICK.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
Remove redundant declaration of youve_print. This probably
had been a review oversight and upstreamed.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
This commit exposes the RTC1 ISR handling function, so the
function can be directly used in tests which generate
customized vector tables manually and require a visible symbol
for the ISR function.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Remove RTOS-2676 from the comment, this is a jira issue number that was
used with zephyr in the past and not available anywhere for reference.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Upcoming Nordic ICs that share many of the peripherals and architecture
with the currently supported nRF5x ones are no longer part of the nRF5
family. In order to accomodate that, rename the SoC family from nrf5 to
nrf, so that it can contain all of the members of the wider Nordic
family.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
On a stm32, When we use the k_busy_wait function to wait a
delay (500us) just after an idle tickless period the delay could be
lower than the requested one. Consecutive readings of the cycle counter
made with the function k_cycle_get_32 juste after tickeless period
provides erroneous values (value jump) after some time (100 us).
To fix this issue we needs:
- Add the update of clock_accumulated_count value in the
_timer_idle_exit function.
- Treat the case in the get_elapsed_count function when the reload value
of the timer is set to a remaining value to wait until end of tick (see
_timer_idle_exit) . In this case the time elapsed until the systick
timer restart was not yet added to clock_accumulated_count. To retrieve
a correct cycle count we must therefore consider the number of cycle
since current tick period start and not only the cycle number since the
timer restart.
Fixes#6164
Signed-off-by: Holman Greenhand <greenhandholman@gmail.com>
In SMP, the system timer is used for timeslicing on auxiliary CPUs,
but the base system timekeeping via _nano_sys_clock_tick_announce() is
still done on CPU0 only (because the framework isn't prepared for
asynchronous notification yet). Skip processing on CPU1+.
Also, due to a hardware interaction* that is difficult to work around,
timer initialization on the auxiliary CPUs is done at the very end of
the CPU bringup, just before the swap into the scheduler. A
smp_timer_init() API has been added for this purpose.
* On ESP-32, enabling the timer seems to result in a near-synchronous
interrupt being delivered despite my best attempts to keep it
masked, then blowing things up because the CPU record isn't set up
to handle it yet.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The earlier xtensa layer put the timer initialization and update
directly into the interrupt handler, which is... weird. Under asm2,
it's just a regular ISR and needs to do the work in the driver.
Really, this driver needs a bunch of cleanup. The xtensa CPU timer is
two registers and one ISR: a global cycle count register, and a
compare register that will fire the IRQ when they match. There is
*way* too much code here.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The existing hand-written interrupt code is manually calling the timer
ISR, which is sort of silly and about to be replaced. Correctly
declare the ISR with IRQ_CONNECT() so that a conventional interrupt
handling implementation can find it. With current code this is a
noop.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Bugfix in the tickless mode part:
During _time_idle_exit it was not announcing to the kernel the
already passed silent ticks, but it was left for the tick interrupt
itself.
This did not cause any trouble so far as there was only the timer
interrupt in this board.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Added possibility to reconfigure CONFIG_SYS_CLOCK_TICKS_PER_SEC
for the native_posix board (before it could only be 100)
+
Fixed tickless idle support
+
Minor fixes in irq wrapping
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Delete the native timer soft IP driver as we will be reusing
the Altera's HAL drivers for most of the soft IP's.
Add shim driver support for Altera timer system clock soft IP.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.
Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.
This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.
For users that just want to continue their work with minimal
disruption the following should suffice:
Install CMake 3.8.2+
Port any out-of-tree Makefiles to CMake.
Learn the absolute minimum about the new command line interface:
$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..
$ cd build
$ make
PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
Besides the fact that we did not have that for the current supported
boards, that makes sense for this new, virtualized mode, that is meant
to be run on top of full-fledged x86 64 CPUs.
By having xAPIC mode access only, Jailhouse has to intercept those MMIO
reads and writes, in order to examine what they do and arbitrate if it's
safe or not (e.g. not all values are accepted to ICR register). This
means that we can't run away from having a VM-exit event for each and
every access to APIC memory region and this impacts the latency the
guest OS observes over bare metal a lot.
When in x2APIC mode, Jailhouse does not require VM-exits for MSR
accesses other that writes to the ICR register, so the latency the guest
observes is reduced to almost zero.
Here are some outputs of the the command line
$ sudo ./tools/jailhouse cell stats tiny-demo
on a Jailhouse's root cell console, for one of the Zephyr demos using
LOAPIC timers, left for a couple of seconds:
Statistics for tiny-demo cell (x2APIC root, x2APIC inmate)
COUNTER SUM PER SEC
vmexits_total 7 0
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_msr 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xapic 0 0
vmexits_xsetbv 0 0
Statistics for tiny-demo cell (xAPIC root, xAPIC inmate)
COUNTER SUM PER SEC
vmexits_total 4087 40
vmexits_xapic 4080 40
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_msr 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xsetbv 0 0
Statistics for tiny-demo cell (xAPIC root, x2APIC inmate)
COUNTER SUM PER SEC
vmexits_total 4087 40
vmexits_msr 4080 40
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xapic 0 0
vmexits_xsetbv 0 0
See that under x2APIC mode on both Jailhouse/root-cell and guest, the
interruptions from the hypervisor are minimal. That is not the case when
Jailhouse is on xAPIC mode, though. Note also that, as a plus, x2APIC
accesses on the guest will map to xAPIC MMIO on the hypervisor just
fine.
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
nrf SOC uses nrf rtc timer (not sys tick), which is 32kHz,
whereas CPU runs at higher speed (nrf52 runs at 64MHz).
So 32Khz is too slow to measure critical kernel parameters.
This patch does :-
1. Add support for nrf SOC for timing_info benchmarking.
2. Uses SOC timer to measure kernel parameters.
Jira: ZEP-2314
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
The API/Variable names in timing_info looks very speicific to
platform (like systick etc), whereas these variabled are used
across platforms (nrf/arm/quark).
So this patch :-
1. changing API/Variable names to generic one.
2. Creating some of Macros whose implimentation is platform
depenent.
Jira: ZEP-2314
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
Add support for TICKLESS KERNEL in nrf_rtc_timer for Nordic family of
processors. This patch includes :-
1. Programming RTC based on "next timer" value from timeout queue while
A. exiting idle_exit.
B. on RTC interrupt.
2. Impliments some of functions which will be required by sys_clock and
scheduler.
ZEP-1819
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
In Tickeless kernel Platform timekeeping is having error because
"_sys_clock_tick_count" is not getting updated correctly.
Currently "OVERFLOW" Flag (bit 16 in timer control register)
is reset before it is taken into account into _sys_clock_tick_count.
This patch sets a flag as soon as Timer Overflow occues and clears
it when time is accounted into _sys_clock_tick_count.
Jira : ZEP-2217
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
By the time we get to POST_KERNEL, kernel services and kernel objects
should be available for use. This should include timers and the random
number generator, but we don't init the system clock until sometime
during the POST_KERNEL phase. Initialize it earlier.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fix nRF RTC timer from returning more than actual cycles
in _timer_cycle_get_32, under race condition when ISR
announces to kernel.
Jira: ZEP-2229
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
XT_* macros are defined in xtensa HAL headers as xcc intrinsics. gcc
does not have any of these intrinsics. Replace XT_* macros with inline
assembly or provide gcc-compatible definitions.
Change-Id: If823ea8a7898a11a3a8363b17efdba27dee4c6a4
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Add tickless kernel support. Sets timer always in one
shot mode to the time the kernel scheduler needs the
next timer event. Uses mili seconds as the scheduling
time unit.
Jira: ZEP-1817
Change-Id: Ia2e63711cdd9d7d9c241b9ff08a606aa79575012
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Add tickless kernel support. Sets timer always in one
shot mode to the time the kernel scheduler needs the
next timer event. Uses mili seconds as the scheduling
time unit.
Jira: ZEP-1818
Change-Id: I21ce037b571c4c6ff588033a15aa49624cba7a57
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Add tickless kernel support. Sets timer always in one
shot mode to the time the kerneel scheduler needs the
next timer event. Uses mili seconds as the scheduling
time unit.
Jira: ZEP-1816
Change-Id: I85232b572759b9653c6396edc057ff4409525c97
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Update the timer to use the tickless kernel interface
provided by kernel to operate in event based mode. In
this mode, the timer would not generate periodic ticks
and would only be programmed in one shot mode. It would
announce elapsed time in wall time units instead of
ticks. Timer can also be disabled enabling waiting
forever for a non-timer event.
Jira: ZEP-1812
Change-Id: I13110b9fb53b33a9244cc91a3d991f8452d330b1
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Adds event based scheduling logic to the kernel. Updates
management of timeouts, timers, idling etc. based on
time tracked at events rather than periodic ticks. Provides
interfaces for timers to announce and get next timer expiry
based on kernel scheduling decisions involving time slicing
of threads, timeouts and idling. Uses wall time units instead
of ticks in all scheduling activities.
The implementation involves changes in the following areas
1. Management of time in wall units like ms/us instead of ticks
The existing implementation already had an option to configure
number of ticks in a second. The new implementation builds on
top of that feature and provides option to set the size of the
scheduling granurality to mili seconds or micro seconds. This
allows most of the current implementation to be reused. Due to
this re-use and co-existence with tick based kernel, the names
of variables may contain the word "tick". However, in the
tickless kernel implementation, it represents the currently
configured time unit, which would be be mili seconds or
micro seconds. The APIs that take time as a parameter are not
impacted and they continue to pass time in mili seconds.
2. Timers would not be programmed in periodic mode
generating ticks. Instead they would be programmed in one
shot mode to generate events at the time the kernel scheduler
needs to gain control for its scheduling activities like
timers, timeouts, time slicing, idling etc.
3. The scheduler provides interfaces that the timer drivers
use to announce elapsed time and get the next time the scheduler
needs a timer event. It is possible that the scheduler may not
need another timer event, in which case the system would wait
for a non-timer event to wake it up if it is idling.
4. New APIs are defined to be implemented by timer drivers. Also
they need to handler timer events differently. These changes
have been done in the HPET timer driver. In future other timers
that support tickles kernel should implement these APIs as well.
These APIs are to re-program the timer, update and announce
elapsed time.
5. Philosopher and timer_api applications have been enabled to
test tickless kernel. Separate configuration files are created
which define the necessary CONFIG flags. Run these apps using
following command
make pristine && make BOARD=qemu_x86 CONF_FILE=prj_tickless.conf qemu
Jira: ZEP-339 ZEP-1946 ZEP-948
Change-Id: I7d950c31bf1ff929a9066fad42c2f0559a2e5983
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types. This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies. We also convert the PRI printf formatters in the arch
code over to normal formatters.
Jira: ZEP-2051
Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix doxygen comment typos used to generate API docs
Change-Id: I6fd5051c99bdcc731740c92001e525349c254d85
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
CONFIG_* usually come from Kconfig, rename variables that are locally
defined to avoid confusion about where they are set.
Change-Id: I83b8459913c5deb68dc1b9f5386b8934363a6d1f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rearming the riscv machine timer is done by first updating the
mtimecmp low value register. If the low value is updated with a
relatively small value, a timer interrupt can be generated while
updating the mtimecmp high value.
To avoid such a spurious interrupt to occur, disable the timer
interrupt while rearming the timer.
Change-Id: I50ab3f19554a9a8dfe70943b6da0d20be3de88dc
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Clear pending IRQ when starting and restore back the RTC1 state when
disabling sys_clock, to avoid issues when soft rebooting the device or
chainloading another Zephyr image (e.g. mcuboot).
Change-Id: I693d9168196ad2cfb8475ecfa2051eac043b1fbd
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
We need to account for the interrupt happening in the middle
of the calculation.
Issue: ZEP-1546
Change-Id: I193534856d7521cac7ca354d3e5b65e93b984bb1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fixes an unlikely issue that could arise if the RTC handler in the nRF RTC
driver was blocked for more than one sys tick interval. This could lead to
_sys_clock_tick_announce() being called with more than one sys tick when the
kernel did not expect it.
Jira: ZEP-1763
Change-ID: I5608fca6f0ac97a17c1ce452c1c5c67696a49a9a
Signed-off-by: Øyvind Hovdsveen <oyvind.hovdsveen@nordicsemi.no>
The LOAPIC driver was doing this in a way susceptible to a very
nasty race condition: the CCR register could reset and be readable
before the associated interrupt could be delivered.
This resulted in a small window of time where CCR was reset, but
accumulated_cycle_count not updated, causing some calls to
k_cycle_get_32() to appear to jump backwards in time.
Just use the x86 TSC for these cycle timestamps. A divisor may be
provided in cases where the CPU clock speed is some multiple of
the bus speed. Modern x86 CPUs do not change their TSC rate even
when adjusting cpu frequency, so this should be a reliable timing
source.
Issue: ZEP-1546
Change-Id: I441bd8e32af866587a91f306e89e3fa0ece512b5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's possible the timer interrupt could occur when performing the
computation, resulting in incorrect values returned.
It's still possible for bad values to be returned if the function is
called with interrupts locked, but that is only fixable with a second
timer source.
Issue: ZEP-1546
Change-Id: I16d5b04c3e32377f7249eb4fb1bf2f7c22bd0836
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a reworked version of the previous RTC driver. The main
changed is related to the handling _timer_idle_exit() on non-RTC
wake-ups. The previous version didn't announce the elapsed time
to the kernel in _timer_idle_exit(). Additionally, the driver now
makes sure never to announce more idle ticks than the kernel asked
for, since the kernel does not handle negative deltas in its timeout
queues.
Change-Id: I312a357a7ce8f0c22adf5153731064b92870e47e
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
Signed-off-by: Øyvind Hovdsveen <oyvind.hovdsveen@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Some arches may want to define this as an inline function, or
define in core arch code instead of timer driver code.
Unfortunately, this means we need to remove from the footprint
tests, but this is not typically a large function.
Issue: ZEP-1546
Change-Id: Ic0d7a33507da855995838f4703d872cd613a2ca2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
On Nios II the same timer peripheral IP block can't function
as a periodic system timer and a high-resolution timestamp source.
A second timer instance with different configuration is required.
Until that is implemented, just return the accumulated cycle count.
Issue: ZEP-1546
Change-Id: If3dcebdc60334bf3aa0ab45ccd82f1b2531b6bc1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
There are race conditions trying to coordinate the value between
the accumulated_cycle_count (updated at interrupt time) and
trying to compute the delta from the last interrupt using the
mtime registers. An unlucky call could result in the timestamp
appearing to move backwards in time.
the 'mtime' register isn't reset at every interrupt. Since we just
want a cycle counter, report its raw value.
Issue: ZEP-1546
Change-Id: I9f404b33214d6502fea47374fcf0ecbf84ef8136
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This driver was written for v1.5 before the introduction of the function
_sys_clock_final_tick_announce. At that time _sys_idle_elapsed_ticks was reset
to 0 automatically. Now that it is reset by the new function, the driver needed
to be fixed.
Change-Id: I039b4dbacb691aaf992b37e44404abd19a54a833
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
This is needed by next commit as some assembly files handling interrupts use
some options from this file.
This file is not included in next commit to separate code and build system
aptches.
Change-Id: Iff3a8019362599beb0c0058c3169480fa5183c1c
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
Enabling the riscv_machine_timer driver by default for riscv32
causes compilation issues on riscv32 boards (like zedboard_pulpino)
not supporting it.
Boards supporting the driver enable it via their respective
config file.
Change-Id: Ieb0d25fa339834fd386ae2725f40b6b7b72dc52b
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This flag is no longer necessary and TICKLESS_IDLE will be
enabled by default if SYS_POWER_MANAGEMENT is enabled.
Jira: ZEP-1325
Change-Id: Ic6cd4b8dc0a17c6a413cabf6509b215a4558318d
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
riscv defines the machine-mode timer registers that are implemented
by the all riscv SOCs that follow the riscv privileged architecture
specification.
The timer registers implemented in riscv-qemu follow this specification.
To account for future riscv SOCs, reimplement the riscv_qemu_driver by
the riscv_machine_driver.
Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Replace _ScbExcPrioSet with calls to NVIC_SetPriority as it handles both
interrupt and exception priorities. We don't need to shift around the
priority values for NVIC_SetPriority.
Jira: ZEP-1568
Change-Id: Iccd68733c3f7faa82b7ccb17200eef328090b6da
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use the CMSIS NVIC APIs rather than the internal ones
so we can remove them in the future.
Change-Id: I31c2f37bc0aa35668a441f4ef2821b768dd7b817
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove use of __scs structures and defines in place of CMSIS defined
ones. Also, use __ISB() instead of inline asm.
Jira: ZEP-1568
Change-Id: I8798206a12680f6c50105c7c28112632ac9dde50
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The riscv-qemu timer driver does not implement
TICKLESS_IDLE
Change-Id: I3eeb5abb05b3f16b55ab9343c2045295b3010cfd
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The pulpino_timer driver does not implement TICKLESS_IDLE
for the time being.
Change-Id: I0cce8c8a7e203d551a924863462e6c86af4c98ff
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Force-align all variables defined via asm .word to ensure 4-byte
alignment.
The straddled_tick_on_idle_enter variable was a bool, which resolved in
an one-byte quantity. Changing it to a 32-bit integer. It would have
occupied 4 bytes anyway with alignment.
Fixes ZEP-1549.
Change-Id: If5e0aa1a75dbc73d896b44616f059d221fe191c6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
On the nRF5x platforms we need always need the NRF_RTC_TIMER and it
depends on the CLOCK_CONTROL_NRF5. So enable all of these always.
Fixes issues if one tries to build nRF5x platforms w/o CONFIG_BLUETOOTH.
Change-Id: I0f9af785e785f37ec289a935ddf70ee6dec08cd4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
rename NANOKERNEL_TICKLESS_IDLE_SUPPORTED to
TICKLESS_IDLE_SUPPORTED and remove nanokernel occurances in Kconfig
files.
Make TICKLESS_IDLE depend on hardware that supports it.
Change-Id: I6a2e4fb0f7cf4b45475b48e71823ea089ee98759
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
PRINTK was conflicting, reanme to DBG.
Jira: ZEP-953
Change-Id: If5d6ef385c5ed223f6f7eae9bde887ae4a1b946a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
That module is not used anymore: it was introduced pre-Zephyr to add
some kind of awareness when debugging ARM Cortex-M3 code with GDB but
was never really used by anyone. It has bitrotted, and with the recent
move of the tTCS and tNANO data structures to common _kernel and
k_thread, it does not even compile anymore.
Jira: ZEP-1284, ZEP-951
Change-Id: Ic9afed00f4229324fe5d2aa97dc6f1c935953244
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The nRF RTC driver, which is used a system clock driver due to the lack
of SysTick hardware on the SoC, was using too much CPU time in its
_timer_idle_exit() implementation due to the use of 64-bit arithmetical
operations. This was causing the ISR wrapper to add excessive latency to
critical interrupts, causing BLE controller asserts.
This patch addresses the issue by using exclusively RTC ticks instead of
OS ticks, thus avoiding the necessity to convert during
_timer_idle_exit() calls, which are the most critical to interrupt
latency.
In addition the driver is now able to detect setting tick events in the
past due to it being interrupted by a higher priority context, and will
reschedule and trigger the ISR at the same time.
Change-id: I56a3be96b9fdd554c3650012d647af2f0415eb8a
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
When going into DEEP_SLEEP state, the ARC timer
needs to be restored.
This implements the function to restore the timer
after sleep.
As the time spent during sleep is not currently known,
the timer is expired to reschedule the application task.
Jira: ZEP-1224
Change-Id: I22a30d0fd79f177cf166b9a29dc78d68f7d7fbad
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
ccflags-y += -I$(srctree)/kernel/unified/include isn't need so lets
remove it.
Change-Id: I910bbac4a189de965d844f5fc36571e8dcb5705d
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit replaces the nanokernel.h include by kernel.h.
Change-Id: Ib42fbf2d9f77a73c0831f569b3dbbfb342ea2e1d
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
The nRF5x series SoCs do not implement systick, hence we disable
CORTEX_M_SYSTICK.
Instead, use nRF SoC Series NRF_RTC1 for system clock interfaces.
The kernel system clock interface is implemented using the low
power real time counter NRF_RTC1. NRF_RTC0 is used by the BLE
controller.
In addition, cleanup nRF5x series defconfig to be consistent.
Jira: ZEP-742
Jira: ZEP-1308
Jira: ZEP-1315
Change-id: I0f6cc1836fe0820a65f2cbb02cf5ae7e9eb92e1d
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Make the systick feature optional that can be selected by the SoC.
Change-Id: I4a405640b84daecc17fc1882743d3cafb78ff861
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
There was a lot of duplication between architectures for the definition
of threads and the "nanokernel" guts. These have been consolidated.
Now, a common file kernel/unified/include/kernel_structs.h holds the
common definitions. Architectures provide two files to complement it:
kernel_arch_data.h and kernel_arch_func.h. The first one contains at
least the struct _thread_arch and struct _kernel_arch data structures,
as well as the struct _callee_saved and struct _caller_saved register
layouts. The second file contains anything that needs what is provided
by the common stuff in kernel_structs.h. Those two files are only meant
to be included in kernel_structs.h in very specific locations.
The thread data structure has been separated into three major parts:
common struct _thread_base and struct k_thread, and arch-specific struct
_thread_arch. The first and third ones are included in the second.
The struct s_NANO data structure has been split into two: common struct
_kernel and arch-specific struct _kernel_arch. The latter is included in
the former.
Offsets files have also changed: nano_offsets.h has been renamed
kernel_offsets.h and is still included by the arch-specific offsets.c.
Also, since the thread and kernel data structures are now made of
sub-structures, offsets have to be added to make up the full offset.
Some of these additions have been consolidated in shorter symbols,
available from kernel/unified/include/offsets_short.h, which includes an
arch-specific offsets_arch_short.h. Most of the code include
offsets_short.h now instead of offsets.h.
Change-Id: I084645cb7e6db8db69aeaaf162963fe157045d5a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
MVIC does not have _REG_TIMER_CFG defined because it does
not have a timer config register. Add checks for MVIC at
places where it is used.
Jira: ZEP-1015
Change-Id: I59f5c43cc2d1b17cf9e88b940631c2542e9729ab
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Interrupt stubs now just push the ISR and parameter onto the stack
and jump to the common interrupt code, never to return.
Change-Id: I82543d8148b5c7dfe116c43f41791f852614bb28
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Update the power sample and drivers with the new device driver power
management API using the existing logic
Jira: ZEP-954
Change-Id: Idd94232e458767635973e94e9fc673c01612c1e2
Signed-off-by: Amir Kaplan <amir.kaplan@intel.com>
Removed CONFIG_INT_LATENCY_BENCHMARK dead code.
CONFIG_INT_LATENCY_BENCHMARK depends on ARCH="x86", it will never
be true for ARM code.
Change-Id: Ia5779a69b1bf670ebb140c2923c9fe0af6b781d4
Signed-off-by: Javier B Perez <javier.b.perez.hernandez@intel.com>
Removed unused workaround in loapic. There are no references
of usage.
Change-Id: I8700b4b7ce8efef5e7b95e6cdd2b201eae3f1f37
Signed-off-by: Javier B Perez <javier.b.perez.hernandez@intel.com>
They must provide the k_cycles_get_32() API and must not refer to
command packets: the latter do not exist on unified kernels.
Change-Id: Ia354dc060e5ad2595850f97da82d8feb590d16b7
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
DEFINE_DEVICE_PM macro was not defining device_pm_ops
as 'static'. Fixes the issue and impacted areas.
Jira: ZEP-639
Change-Id: I5e1de6af97bf7b2b690af0c81034ce167e655e43
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Originally, x86 just supported APIC. Then later support
for the Mint Valley Interrupt Controller was added. This
controller is mostly similar to the APIC with some differences,
but was integrated in a somewhat hacked-up fashion.
Now we define irq_controller.h, which is a layer of abstraction
between the core arch code and the interrupt controller
implementation.
Contents of the API:
- Controllers with a fixed irq-to-vector mapping define
_IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time
map between the two.
- _irq_controller_program() notifies the interrupt controller
what vector will be used for a particular IRQ along with triggering
flags
- _irq_controller_isr_vector_get() reports the vector number of
the IRQ currently being serviced
- In assembly language domain, _irq_controller_eoi implements
EOI handling.
- Since triggering options can vary, some common defines for
triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH,
IRQ_POLARITY_LOW introduced.
Specific changes made:
- New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers
that have a fixed relationship between IRQ lines and IDT vectors.
- MVIC driver rewritten per the HAS instead of the tortuous methods
used to get it to behave like LOAPIC. We are no longer writing values
to reserved registers. Additional assertions added.
- Some cleanup in the loapic_timer driver to make the MVIC differences
clearer.
- Unused APIs removed, or folded into calling code when used just once.
- MVIC doesn't bother to write a -1 to the intList priority field since
it gets ignored anyway
Issue: ZEP-48
Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Defined in all SoCs, but never referenced anywhere. That definition has
been replaced by CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
Change-Id: I1801f72a03925717ded6fbfdef22b1993f843461
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
A previous re-work of IRQ priorities was led astray by an incorrect
comment. Priority level 1 is not a non-maskable interrupt priority.
In addition, zero latency IRQs are not implemented on ARC.
Timer driver now doesn't specify IRQ_ZERO_LATENCY (as that wouldn't be
correct) and its IRQ priority is now tunable in Kconfig. The default is 0.
IPM driver on both ARC and x86 side were being configured with hard-coded
priority of 2, which wasn't valid for ARC and caused an assertion failure.
The priority level is now tunable with Kconfig and defaults to 1 for ARC.
Issue: ZEP-693
Change-Id: If76dbfee214be7630d787be0bce4549a1ecbcb5b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We have already done this on x86 and ARM. The policy is as follows:
* IRQ priority levels starting at 0 all have the same semantics and
do not have special properties. The priority level is either ignored
on arches which do not support programmable priority levels, or lower
priority levels take precedence over higher ones.
* Special-case priorty levels are specified via flags, in which case
the supplied priority level is ignored.
Issue: ZEP-60
Change-Id: Ic603f49299ee1426fb9350ca29d0b8ef96a1d53a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is part of a change to enable device suspend/resume and
Deep Sleep support in applications. Adds suspend/resume handling
in loapic timer.
Jira: ZEP-512
Change-Id: I9da2c8419bd9109fb71ef5a6caf736de7c7de9e1
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Tickless idle is not yet supported. We program the timer period
to the desired system clock tick rate (sys_clock_hw_cycles_per_tick).
This was renamed to the same name used in the Altera Embedded IP
Peripherals Guide; used by other CPUs than Nios II.
Change-Id: Ic4fca8c16b923295b77b63f98f45cd3483c5f560
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Building microkernel for ARC causes a compiler error
due to missing declaration of _sys_idle_elapsed_ticks.
Declare this as extern.
Jira: ZEP-397
Change-Id: I83701f693fea0fcb1ae2c30e0c52abe7987de1f1
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
The timer implementation for ARC currently requires timer0 to be present.
I've added a comment that this is an assumption and to encourage developers
to build the ARC CPU with Timer0, when it is to be used with Zephyr.
There is also an optional provision for a Timer1. In future, this
code could be conditional to use either timer.
Change-Id: I4eb3aec59ba4e85f8b70d5531b21bdaab00b93bb
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Basic build framework for Nios2. Everything is stubbed out,
we just want to have a build going so that we can start to
parallelize implementation tasks.
This patch is not intended to be functional, but should be
able to produce a binary for all the nanokernel-based
sanity checks.
Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Changed names of Kconfig flags, variables, functions, files and
return codes consistent with names used in the RFC. Updated
relevant comments to match the changes.
Origin: Original
Change-Id: Ie7941032d7ad7af61fc02928f74538745e7966e8
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for task_sleep() and fiber_sleep() during the
system initialization. When CONFIG_NANO_TIMEOUTS defined,
before the k_server() starts, kernel uses nanokernel
system clock announce and task sleep functionality.
To give device drivers early sleep functionality, the system
clock has to start on SECONDARY initialization level, same
as most of the drivers.
Change-Id: Ie1d391945cd1cfb9a5dc199783c2d224eb1b0ef3
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
ASSERT are put each time the timer0 limit register or the timer0 count register
is modified.
Change-Id: I38684d57803de285f4e26c68b449c71396e4c750
Signed-off-by: Simon Desfarges <simon.desfarges@intel.com>
When exiting from tickless idle uppon an external IRQ, the TICK timer
is set to fire at next TICK boundary. The current algorithm can lead
to a point that timer0_count register is higher than the timer0_limit
register.
In this situation the next TICK will fire after the counter has
wrapped and performed another cycle (~133 seconds).
This condition appears when the counter reaches the limit after the
Interrupt Pending flag is checked. At this point the counter is
automatically wrapped to 0, but is set just next to the limit to fire
at next TICK boundary by SW. At exit of the _timer_idle_exit function,
the timer handler is called, and sets the limit to 1 TICK. At this
point the situation is:
- limit register == 1 TICK
- count register is just below the old limit register and higher than
1 TICK
To fix this issue, at _timer_idle_exit, the limit register is always
set to 1 TICK and the count register set such as the next TICK fires
on time.
Change-Id: Ifa002809d426aa04109592e53d2b02a224f51101
Signed-off-by: Simon Desfarges <simon.desfarges@intel.com>
The timer counts from 0 to programmed_limit included.
Change-Id: Ifc8585210c319f5452fafc911d4f6d72c4b91eaa
Signed-off-by: Simon Desfarges <simon.desfarges@intel.com>
This reverts commit 0d50329105.
This breaks sanitychecks in CI. The early_sleep kernel test case is failing
randomly.
Change-Id: I015f20699c052b4089076699fc0180945c4d3d16
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for task_sleep() and fiber_sleep() during the
system initialization. When CONFIG_NANO_TIMEOUTS defined,
before the k_server() starts, kernel uses nanokernel
system clock announce and task sleep functionality.
To give device drivers early sleep functionality, the system
clock has to start on SECONDARY initialization level, same
as most of the drivers.
Change-Id: I5b3cf3da4c8d8398a966e901ab211f2fcee18dd6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
This reverts commit 3c66686a43.
That commit fixed announcing ticks before the microkernel was up, but
prevented devices initializing before the MICROKERNEL level from having
access to the hi-res part of the system clock, which they could not poll
anymore.
Change-Id: Ia1c55d482e63d295160942f97ebc8e8afd1e8315
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Modifications to timer drivers and interrupt setup, to manage
the tickless idle for the x86 architecture
Change-Id: Ie02d484b7e5636de6ea382ba2eeed57e704c8498
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
The ticker was always initialized in the NANOKERNEL init level. In a
microkernel, this can cause problems if for the some reason the
initialization of the microkernel server is delayed, such as devices
initialization in the NANOKERNEL level taking non-insignificant time to
complete. What happens in that case is the ticker ISR will start firing
and piling up events in the microkernel server stack, and quite quickly
overrun it, since it has a finite size, causing random crashes.
So, in the microkernel, initialize the ticker once the microkernel
server is available. There is no point in sending ticker event before
anyway.
Change-Id: Ie9e13184f6ad35954023faf3bbff26242284b7be
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
It's not a function and requires all its arguments to be build-time
constants. Make this more obvious to the end user to ease confusion.
Change-Id: I64107cf4d9db9f0e853026ce78e477060570fe6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Mostly SoC initialization and some kernel subsystems, but also some
device drivers like the interrupt controllers.
Change-Id: I8dc1844c33acd877c075b6b03558fdca6f87500b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This is the last step before obsoleting DEVICE_DEFINE() and
DEVICE_INIT_CONFIG_DEFINE().
Change-Id: Ica4257662969048083ab9839872b4b437b8b351b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_DEFINE() so that it fits in the 'device' namespace.
Change-Id: I3af3a39cf9154359b31d22729d0db9f710cd202b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_INIT_CONFIG_DEFINE(), because (a) it was not fitting
in any namespace and (b) it is not used to declare, but rather define a
object.
Change-Id: I1da5822f06b85a9fb024b5b184afd0ccc01012ec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
On NANOKERNEL level only of course. Some devices, initialized at this
level, may require to get the clock running already.
Change-Id: Id2dd830d915474aac6c080068c2cf356cf841e0c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The interrupt API has been redesigned:
- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
It will be used in situations where the new static irq_connect()
won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
exactly the same way as its dynamic counterpart. The old static irq
macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
generated inline with irq_connect()
ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.
Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
