This gets rid of the z_ prefix.
Note that z_xt_*() are being used by the HAL so they cannot be
renamed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The plic has a very simple mechanism to claim an interrupt as well as to
complete and clear it. The same register is read from/ written to to
achieve this.
Get the ID of the HART that serviced the interrupt and write to the
claim complete register in the correct context
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
The plic uses contexts to seperate irq enables, threshold priority and
claim complete registers from each core for a given platform. As well as
this, each privilege level has its own context.
for multi-core platform's, we need to be able to enable/ disable a
global interrupt for all the cores that are associated with Zephyr.
To do this, we need to make some assumptions:
1. The privilege contexts are contiguous
2. M mode context is first, followed by S mode.
We know how many cpus are used in an application and each cpu's hartid,
thanks to some very handy inline functions. So we iterate through each
cpu and use the hartid of a cpu in the calculation of the context.
While we are at it, In an effort to make the driver more readable,
allign with the macro naming convention outlined in Linux's PLIC driver
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Multilevel interrupt configs are leaking into every single build without
this option being enabled, so guard the Kconfig and include files to
avoid this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Define the edge-trigger register base address based on whether
the PLIC node in the devicetree has an additional compatible
that supports edge-triggered interrupt.
Limited the implementation to Andes NCEPLIC100 only, updated
the devicetree binding of `andes_v5_ae350` accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This commit introduces a new interrupt controller driver used
for NXP's IRQ_STEER IP.
Apart from introducing the driver itself, this commit contains
the following changes:
1) Switch i.MX8MP to using the XTENSA core interrupt
controller instead of the dummy irqsteer one.
* this is required because the binding for the
irqsteer driver is no longer a dummy one
(since it's being used by the irqsteer driver).
As such, to avoid having problems, switch to
using another dummy binding.
2) Modify the irqsteer dummy binding such that it
serves the IRQ_STEER driver's needs.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
There's a ternary operator that depends on configuration-defined macro:
`CONFIG_DYNAMIC_INTERRUPTS` is not enabled by default
for any of the platforms that use PLIC,
it is possbile to set it to `=y` though.
This triggered the Coverity check to report it as dead code.
Fixes#65576.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
The `riscv_plic_irq_enable` & `riscv_plic_irq_disable` are very
similar, refactor them out into `plic_irq_enable_set_state`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Introduced `CONFIG_PLIC_SHELL` to enable the build of shell
debugging command to get the hit count of each interrupt
controller's IRQ line. This is especially useful when working
with dynamically installed ISRs, which will be the case for
`plic_sw`.
Example usage:
```
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits
==================
10 177
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits
==================
10 236
uart:~$ plic stats clear interrupt-controller@c000000
Cleared stats of interrupt-controller@c000000.
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits
==================
10 90
```
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Maxim Adelman <imax@meta.com>
if-conditionals should have brackets according to Zephyr's
coding standard, and explicitly compares `edge_irq` against 0.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Previously, the PLIC's registers were accessed through uint32_t *,
so all calculated offsets were effectively multiplied by
sizeof(uint32_t). Do the same manuallly now that we have
mem_addr_t/sys_read32.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
`get_claim_complete_offset` and `get_threshold_priority_offset` actually
return addresses directly. Rename them to `_addr` for consistency within
the driver. Also change their return type to `mem_addr_t`.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
Use arch-specific sys IO APIs to access the memory-mapped
registers to ensure safe memory operations
fixes#62956
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Added some defines and helper functions to help with the
arithmetics so that the bit shifts and stuff do not look like
magic number.
Converted manual bit shift/set/unset to use macros provided by
Zephyr.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Most of the public APIs in `riscv_plic.h`
(except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the
`irq` argument to be in Zephyr-encoded format, instead of the
previously `irq_from_level_2`-stripped version. The first level
IRQ is needed by `intc_plic` to differentiate between the
parent interrupt controllers, so that correct ISR offset can be
obtained using the LUT in `sw_isr_common`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Use a config struct to store per-instance device config during
init and connect the IRQ based on the devicetree instead of
hardcoded value and instance number.
The `get_plic_dev_from_irq` is still a placeholder for now and
always return the first instance.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Some NXP S32 shim drivers are using macros defined in
soc/arm/nxp_s32/*/soc.h but not including soc.h. Those still
can be built because the header file is included indirectly
by some other header files. This is very fragile, it should
be included directly
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics.
Note that for some peripheral instances is needed to define the
HAL macros of the peripheral base address because there are gaps
in the instances or there are SoCs with a single instance.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Relocate multi-level interrupts APIs out of `irq.h` into
a new file named `irq_multilevel.h` to provide cleaner
separation between typical irq & multilevel ones.
Added preprocessor versions of `irq_to_level_x` as `IRQ_TO_Lx`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Remove the HWSEM locking around stm32_exti_disable().
The STM32 EXTI driver uses the core-local interrupt mask regsiters on
STM32H7x7 asym. dualcore MCUs. There is no need to lock the HWSEM
guarding the EXTI when accessing these registers.
Some sensor drivers toggle their interrupt mask every time the sensor
triggers the IRQ line. Locking the HWSEM fails e.g. in situations where
one coprocessor serivces the sensor and the other coprocessor sets up
its interrupts initially during bootup. This prevents the sensor driver
from locking the HWSEM and causes a kernel panic on the corresponding
CPU.
Note: The opposing stm32_exti_enable() was already correctly without
locking.
Signed-off-by: Martin Gritzan <martin.gritzan@gmail.com>
Introduce an interrupt controller for the NXP S32 WKPU peripheral
that can be integrated with GPIO to trigger interrupts through
external interrupt pad inputs.
WKPU can trigger interrupts from certain input pads that support this
function, as well as wake-up events to the power management domain. This
patch only adds WKPU functionality as an interrupt controller to extend
the number of input pads that can interrupt the core. Power management
functionalities are not supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Define all the register offset directly in the driver according
to the RISCV PLIC specification as they are not configurable,
see: https://github.com/riscv/riscv-plic-spec.
Updated devicetrees that has PLIC accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Removing the edge-trigger Kconfig as it is supported by default
in the RISCV PLIC specifications.
Define the edge-trigger register offset in the driver instead
of retrieving the value from devicetree as it is not something
configurable. The value 0x1080 is defined in Andes & Telink
datasheets.
Updated build_all testcase.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
NOCACHE_MEMORY depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT, so
don't try to select the symbol if not supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert DEVICE_DEFINE to DEVICE_DT_INST_DEFINE, this allows the build
system to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Adjust some DT_INST macro as well while at it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Fix an incorrectly declared compatible and adjust some DT macros as
well.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit follows the parent commit work.
This commit introduces the following major changes.
1. Move all directories and files in 'include/zephyr/arch/arm/aarch32'
to the 'include/zephyr/arch/arm' directory.
2. Change the path string which is influenced by the changement 1.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Use DEVICE_DT_INST_DEFINE instead of DEVICE_DEFINE to declare the device
structure. This ensures that the device gets an ordinal and is
initialized before any device depending on it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The old acpi implimentation is replaced with acpica interface
and updated x86 arch porting with the new interface.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
Add TI VIM (Vectored Interrupt Manager) interrupt controller support.
VIM is a TI specific custom interrupt controller for ARM cores.
In J721E soc, VIM aggregates interrupts to Cortex R5 cores.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
VIM: section 6.3.3.6
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
As per #26393, Local APIC is using Kconfig based option for
the base address. This patch adds DTS binding support in the driver,
just like its conunter part I/O APIC.
Signed-off-by: Umar Nisar <umar.nisar@intel.com>
GIC-600 and later interrupt controllers have an additional
GICR_PWRR register that controls the power up sequencing
of the redistributors. Added logic to gicv3_rdist_enable to
configure GICR_PWRR if required.
Signed-off-by: Chad Karaginides <quic_chadk@quicinc.com>
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).
To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.
All files including CMSIS have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
