The clock controller/manager registers are updated with
the correct divider values by bootloader via hand-off
data, so now we can use the clock controller to get the
clock value of each peripheral during the run time.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Add a function to compute the clock48 from the clock tree
of a stm32f412/f413 mcu. The value depends on its clock source
Requires to identify the PLL source HSE or HSI.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the configuration of the PLL Q divider of main PLL
and I2S_Q of the PLLI2S toset the PLL48MHz clock which feeds
the USB, SDMMC, RNG through the RCC_DCKCFGR2 register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Implement the zero latency interrupt safe APIs to the HFXO clock
commonly used by the bluetooth stach from zero latency interrupt
context.
Co-authored-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
It may be required to get information if NRF LF clock control calibration
is in progress. Some time sensitive operations could benefit from this
information.
The commit adds simple function that provides the information.
The function is nRF platform specific.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Update init function so APPCPU could not altere the clock setup.
Fix build in case if no inter-cpu module is selected.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Support specifying divided clock buses by introduction of
STM32_CLOCK_DIV(div) macro. This macro can be used in devicetree to define
clock source of peripherals.
HSE is selected in devicetree using:
<&rcc STM32_SRC_HSE ...>;
HSE/2 can now be selected with:
<&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) ...>;
This allows to use clock_control_get_rate() API in peripherals in order to
get desired clock rate.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Due to clock designed on RT1180 has some different with other platforms,
so add macro and handle the clock difference in mcux_ccm_get_subsys_rate.
TPM1 use Bus_Aon as clock root.
TPM3 use Bus_Wakeup as clock root.
Other instances have independent clock root.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Rely on the DTS to get the MCO input source clock and prescaler.
DTS configuration has been introduced and Kconfig method
deprecated two releases before and can be then safely removed.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32F41x have a PLLI2S M divider for their PLL I2S
but others like the stm32F401 or stm32F74x have the PLL M
divider from the main PLL : might affect the sysclock.
LL Function is the same for configuring the PLL I2S but
parameter could depends on the stm32 serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
No in-tree board uses this driver's pinctrl functionality, and every
RP2040-based board was configuring this to be an empty node in the
device tree, so remove them.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
RESETS_RESET_PLL_USB_BITS was logically or'd twice and 'unreset'ting
PWM doesn't seem to be required, based on the contents of the SDK.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Due to the possibility of simultaneous accesess to LRCCONF registers,
additional management is required.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
This commit adds the clock driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
The `Kconfig.defconfig` is not good place for put `select PINCTRL`.
Drop `select PINCTL` from `Kconfig.defconfig` and add it at each
driver's Kconfig.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The NXP PORT pinmuxing peripheral is reused across the MCX, S32, and
Kinetis lines. Rename the compatible from the family-specific
nxp,kinetis-pinctrl to a more generic nxp,port-pinctrl to reflect the
actual name for the IP block used within reference manuals.
Update the NXP HAL revision to include a change to use the new Kconfig
name for the PORT pinctrl driver
Update the MAINTAINERS.yml path, as there are no longer any NXP drivers
matching the string "drivers/*/*kinetis*
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove the renesas,ra-clock-generation-circuit driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Disable every PLL before configuration. That allows
an application to reconfigure PLLs after a bootloader
configuration.
Don't disable the PLL clock if it is used by (Q|O)SPI
when executing from external memory. That will lead
to a stall.
Note: when (Q|O)SPI runs from PLL, the bootloader
dictates the clock configuration. There is no clock
reconfiguration support for memory map mode in
(Q|O)SPI drivers.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Add npcm clock control driver.
Signed-off-by: James Chiang <cpchiang1@nuvoton.com>
Signed-off-by: Joseph Liu <kwliu@nuvoton.com>
Signed-off-by: Alan Yang <tyang1@nuvoton.com>
The new update of clock device tree make the pll p q r clock
source cannot be choose by other node
This fix add 1 new dts binding for pll out p q r out line
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Instead of fixing csi2rx clock frequencies, set them according to the
pixel rate got from the camera sensor.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Enabled the MRT at the board level for
mcxn947. Enabled the clocking for the MRT
in the clock control.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
To check if DVFS can be used, the CONFIG_NRFS_DVFS_LOCAL_DOMAIN symbol
needs to be used, not CONFIG_NRFS_HAS_DVFS_SERVICE which only indicates
that DVFS is technically possible, not that its local domain part is
actually included in the build.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit 7a2ce2882a.
Do not enable clock control by default on nRF54H Series SoCs when
the system timer is present, because clock control is not needed
for this purpose there.
Add missing `default y` in the CLOCK_CONTROL_NRF2 Kconfig option that
enables compilation of clock control drivers for nRF54H Series.
This way modules that actually require clock control (like drivers
that use radio) will be able to enable it using the generic option
(CLOCK_CONTROL), not the above one that is specific for nRF54H.
Update accordingly applications that referenced the CLOCK_CONTROL_NRF2
option.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The Drivers using Pinctrl should be turning Pinctrl on
this should not be the responsibility of the board. This
commit removes CONFIG_PINCTRL from the boards side for nxp boards.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
STM32C0 have a different prescaler for SYSCLK and for HCLK.
Updates the clock driver to use the appropriate prescaler for each series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fixes garbage characters on mcuboot by adjusting UART baudrate
during boot phase according to clock source.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Adding the macros `RA_CGC_CLK_SRC` and `RA_CGC_CLK_DIV` that derive
the BSP clock settings from the DeviceTree node settings.
I also define some aliases to fill in the gaps with the BSP
naming conventions.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This will calibrate the HSI's PLLX clocks if enabled
The value rcc_hsicalibartion_default is 0x40U for h7/h7rs.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
