Default enable WIFI_NM for both supplicant and embedded supplicant
case, to distinguish STA and SAP interface when use L2 layer.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
These device driver APIs were merged after the DEVICE_API macro was
introduced.
Cleanup these leftover drivers.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The clock controller/manager registers are updated with
the correct divider values by bootloader via hand-off
data, so now we can use the clock controller to get the
clock value of each peripheral during the run time.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Prevent the driver from perfroming transfer when SPI_LINES_OCTAL flag
is specified, as this driver supports only SPI_LINES_DUAL for now.
Signed-off-by: Michal Morsisko <morsisko@gmail.com>
Add support for sending and receiving the least significant bit first
for the spi_bitbang driver. This driver can now be used with
SPI_TRANFER_LSB flag.
Signed-off-by: Michal Morsisko <morsisko@gmail.com>
The actual clock speed of the bus is partially determined by the
rising/falling edges of the SCL. These settings allow applications
to tune the clock based on board characteristics.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
Enable the device runtime power management on the SPIM shim.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Kconfig names follow the convention CONFIG_I2C_driver-name. Rename
RENESAS_RA_I2C_IIC to I2C_RENESAS_RA_IIC to align this config name
with all others.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Originally, when the timer's source clock is 32.768 kHz, the timer driver
uses two consecutive reads to ensure the timer reading is correct.
However, it is not robust enough due to an asynchronous timing issue in
the chip. The workaround is to add at least two NOPs between the
LDR and CMP instructions. This commit implements the workaround in the
assembly code to ensure it is not affected by the compiler toolchain
or optimization flags.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit aims to improve the integration of `esp_wifi_drv` by
providing the link mode information to `wifi_mgmt` when a station device
is connected to the AP.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Compilation will fail if multiple models are used at the same time.
Changing to define different unique names for the symbols
to avoid conflicts.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Use HEAP_MEM_POOL_ADD_SIZE_ to add heap for NXP Wi-Fi. For supplicant
case, define less heap, as CONFIG_HEAP_MEM_POOL_ADD_SIZE_HOSTAP and
CONFIG_HEAP_MEM_POOL_ADD_SIZE_SOCKETPAIR are also enabled.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
Set TWT response parameters to zero to avoid
uninitialized values and ensure correct behavior.
Signed-off-by: Triveni Danda <triveni.danda@nordicsemi.no>
Currently, MT25 flashes were running in 3-byte mode.
This is not compatible with the chip we use in our project (MT25QU01GBBB),
as only 128 Mbit of its 1 Gbit can be addressed.
Signed-off-by: Martin Stumpf <finomnis@gmail.com>
To facilitate changing this driver, decouple rtio from functions not
specific to RTIO. This also requires moving the sdk driver handle
creation outside of the configure call. An effect of this is we can
stop initializing an unused sdk driver handle for the dma path.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
These changes:
* Fix the check of the word size to be more useful
- check min frame size instead of max
- check for min word size requirement
- add a clarifying comment about what the word size represents in
hardware since the nomenclature from zephyr does not match the nxp
references
* Add a clarifying comment about half duplex being supported by hardware
* Add LPSPI_ namespace to defines
* Change chip select error message to be more clear about the problem
* Move the check of the clock device being ready to the lpspi init,
instead of checking it every time on configure. It probably also makes
more sense to not ready the lpspi device if the clock is not ready.
* Move the bare-metal configuration of bit fields AFTER the SDK Init
call.
* Return the proper error code if clock control call errors.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Compilation will fail if both adin2111 and adin1100 are used
at the same time.
Changing to define different unique names for the symbols
to avoid conflicts.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Resets uart tx fifo during driver initialization to have a well defined
initial condition mainly preventing unwanted characters being sent
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
No need for an extra step to enable feature in the driver as it clearly
depends on the supplicant feature.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Add a function to compute the clock48 from the clock tree
of a stm32f412/f413 mcu. The value depends on its clock source
Requires to identify the PLL source HSE or HSI.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the configuration of the PLL Q divider of main PLL
and I2S_Q of the PLLI2S toset the PLL48MHz clock which feeds
the USB, SDMMC, RNG through the RCC_DCKCFGR2 register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
