It is just used to be able to DEVICE_DT_GET() bus devices from
tests/drivers/build_all in an upcoming commit.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Corrected comapare value of dma_is_enabled as it is compare with
wrong macro to check if channel is enabled or not.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Enhance LPSS DMA to support UART and I2C DMA transfer by
enabling init priority of DMA based on dependency on
parent device.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Replace unrelated part name with the actual driver name in the
adxl372.h header file.
Fixes: a3e7cea ("adxl372: Add driver for ADXL372 high-g accelerometer")
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
'native_posix_source_files' is used only when CONFIG_NATIVE_APPLICATION=y,
but it was set unconditionally regardless of this Kconfig option.
Set 'native_posix_source_files' under CONFIG_NATIVE_APPLICATION=y to narrow
scope of this variable.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Affected CONFIG_ADC_ADS114S0X_GPIO=y build.
register_addresses was wrong type for
ads114s0x_write_multiple_registers()
Signed-off-by: Nick Ward <nix.ward@gmail.com>
Move all the generic code from the Nuvoton NPCX keyboard scanning driver
into input_kbd_matrix.c. While doing that convert few configs into
devicetree properties and tweak few other things to enable the generic
code to support multiple instances.
This is limited to 8 rows for now, and that's fine for all the current
in-tree drivers, the limit could be removed down the road but this
should be fine for now, added few generic build checks to make sure a
driver does not go over the limit, as well and some more implementation
specific checks.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
For example, if a driver needed to reserve address before it does a
ENTDAA, it would need to get free address in a loop, but the get
free address func would return the same address everytime. It needs
the start address, which would be the last free address it go, to
be passed in to get the next free address.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Add pinctrl to the Davinci GPIO driver to allow muxing pins dirctly
in this driver.
Also aligned the macro backslashes as line continuation character at
the end of each line with each at the same position and removed the
GPIO_DAVINCI_DEVICE_INIT macro which seems to be not used.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Sort the Kconfig and CMakeLists include blocks again, and mark the start
and end of the blocks so that the CI can keep them sorted.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
- Add support cc1352p7 used by beagleconnect_freedom
- Since this is a multi interface device, auto config does not work.
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
Having a % FIFO watermark isn't very useful as it doesn't convey how long
the SoC can sleep (or do other work) while batching sensor data. Convert
the attribute to a batch duration using ticks. Currently the ticks are
in system ticks, but eventually when an external clock is attached to
the sensor it will be in the external clock's ticks.
Signed-off-by: Yuval Peress <peress@google.com>
Add streaming implementation for icm42688 using both threshold and
full FIFO triggers.
Signed-off-by: Yuval Peress <peress@google.com>
topic#sensor_stream
Introduce a streaming API that uses the same data path as the async API.
This includes features to the decoder:
* Checking if triggers are present
Adding streaming features built ontop of existing triggers:
* Adding 3 operations to be done on a trigger
* include - include the data with the trigger information
* nop - do nothing
* drop - drop the data (flush)
* Add a new sensor_stream() API to mirror sensor_read() but add an
optional handler to be able to cancel the stream.
Signed-off-by: Yuval Peress <peress@google.com>
topic#sensor_stream
Convert the ITE keyboard scanning driver from kscan to input, add the
corresponding kscan compatibility node to the current board, build test
only.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Use GPIO_OUTPUT_INACTIVE to initialize the pin so that the ACTIVE_LOW DT
flag is honored and use the gpio_pin_set_dt functions to set the
(logical) value of the pin instead of gpio_pin_configure_dt, that
tries to reconfigure the pin each time.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Initialize the MDIO peripheral clock (normally done during GMAC
initialization) before trying any MDIO transfers, preventing startup
errors.
Signed-off-by: Nick Kraus <nick@nckraus.com>
We need to do a build assert for the fifo enable status of 'I2C2'.
There is a problem with using instance to obtain property when
any one I2C port is not enabled.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit enables clock control on the i.MX8QM and QXP boards.
This is achieved through the following changes:
1) The "reg" property is no longer marked as required
for the "nxp,imx-ccm" binding. This is necessary because
in the case of i.MX8QM and i.MX8QXP the clock management
is done through the SCFW, hence there's no need to access
CCM's MMIO space (not that you could anyways).
2) The DTS now contains a scu_mu node. This node refers
to the MU instance used by the DSP to communicate with
the SCFW.
3) The CCM driver needs to support the LPUART clocks
(which will be the only IP that's supported for now)
and needs to perform an initialization so that the
NXP HAL driver knows which MU to use to communicate
with the SCFW.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Use arch-specific sys IO APIs to access the memory-mapped
registers to ensure safe memory operations
fixes#62956
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Added some defines and helper functions to help with the
arithmetics so that the bit shifts and stuff do not look like
magic number.
Converted manual bit shift/set/unset to use macros provided by
Zephyr.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Most of the public APIs in `riscv_plic.h`
(except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the
`irq` argument to be in Zephyr-encoded format, instead of the
previously `irq_from_level_2`-stripped version. The first level
IRQ is needed by `intc_plic` to differentiate between the
parent interrupt controllers, so that correct ISR offset can be
obtained using the LUT in `sw_isr_common`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Use a config struct to store per-instance device config during
init and connect the IRQ based on the devicetree instead of
hardcoded value and instance number.
The `get_plic_dev_from_irq` is still a placeholder for now and
always return the first instance.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Many (or almost all) drivers contain the specified prefixes
related to the driver subsys so add the missing one for the
BQ24190.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
This patch set provides support for T1S ethernet device - LAN8651.
For SPI communication the implementation of Open Alliance TC6
specification is used.
The driver implementation focuses mostly on reducing memory footprint,
as the used SoC (STM32G491) for development has only 32 KiB RAM in total.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Those files provide generic functions to handle transmission between chip
conforming OA TC6 standard and Zephyr's network stack represented by
struct net_pkt.
The communication is performed via SPI and is focused on reduced memory
footprint (works with SOC equipped with 32 KiB of RAM) and robustness of
operation.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
ep_ctrl and ep_trans_type is not used inside it82xx2_usb_dc_isr, this
triggers a compile warning. Move these variables to a smaller scope.
Signed-off-by: Ting Shen <phoenixshen@google.com>
Add drivers for gpio_i2c_switch which is present in beagleconnect freedom
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
The load switch / LDO pin configuration function now
correctly configures the associated GPIO pin.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
When using console debug server hooks, not all characters are
processed if the server hook returns non-zero for one character
while there are other characters in the buffer. This is seen
when using a fast console (like USB) where multiple characters
come in before the ISR is called. Fix it by continuing to
process characters instead of returning from the ISR with
characters still in the buffer.
Fixes: #64661
Signed-off-by: Mariano Goluboff <mariano.goluboff@nordicsemi.no>
Some NXP S32 shim drivers are using macros defined in
soc/arm/nxp_s32/*/soc.h but not including soc.h. Those still
can be built because the header file is included indirectly
by some other header files. This is very fragile, it should
be included directly
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Remove the depenency on TF-M so that this driver can be used when PSA
is provided by something else than TF-M.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
