This commit adds an additional test case for several kernel test suites
to ensure that the linker script generator is working correctly for a
subset of the Zephyr test suites.
The ensures that the basic functionality of the linker script generator
is working while still keep the performance impact on CI at a minimal
level.
Using the kernel tests is a trade-off between testing coverage of the
linker script generator and the time it takes to complete CI.
The kernel tests is considered to have the broadest coverage of various
features important for the generated linker script.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Add test cases of direct interrupt for arch x86 and posix.
We register two direct interrupt at build time, then triggering
interrupt and check if ISR handler has executed or not. We also
check irq_enable and irq_disable works.
Why we add an extra compiler option "-mgeneral-regs-only" to make
it works in arch x86. because there might be some existing x87
instructions executing inside interrupt context.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
tests/kernel/interrupt tests interrupt trigger functionality,
however, the Non-Secure Cortex-M mode does not have full control
of the interrupt handling, so this test cannot be guaranteed to
pass when executing in Non-Secure mode. Filter the test out for
Non-Secure Cortex-M builds.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
GICv3 is now support for SGI generation and test case is updated
to use GICv3 apis. bcm958402m2_a72 can be enabled now.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
The test itself handles correctly whether gen_isr_table
style dynamic interrupts are supported or not, there's
no need for an alternate scenario.
The tests work fine on riscv32 now, remove the exclusion.
Add a github link as to why Nios II is still excluded.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
There are two set of code supporting x86_64: x86_64 using x32 ABI,
and x86 long mode, and this consolidates both into one x86_64
architecture and SoC supporting truly 64-bit mode.
() Removes the x86_64:x32 architecture and SoC, and replaces
them with the existing x86 long mode arch and SoC.
() Replace qemu_x86_64 with qemu_x86_long as qemu_x86_64.
() Updates samples and tests to remove reference to
qemu_x86_long.
() Renames CONFIG_X86_LONGMODE to CONFIG_X86_64.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
* add the case for ARC in yaml after dynamic and direct irq are
supported
* fix the bug that index in sw_isr_table should have a offset of
CONFIG_GEN_IRQ_START_VECTOR
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
As we have re-worked the test code, and the test-case can run
on Cortex-M platforms on any available and implemented NVIC
IRQ lines, we do not need to exclude these ARM boards anymore.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Platforms which use the GEN_SW_ISR mechanism for interrupt handling
can make use of a really simple whitebox trick for verifying that it
worked (i.e. that the pointer and argument get placed in the table
correctly).
Easy and simple way to get some coverage for dynamic IRQs, which is
currently entirely missing. Long term we'll want to replace this with
a test that uses the API directly and chooses an arch-specific vector
to set, and triggers it using arch-specific code, but that's quite a
bit more effort and for now we need to land patches to
z_irq_connect_dynamic() which show test coverage.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Exclude the two variants of smt32_min_dev (stm32_min_dev_black and
stm32_min_dev_blue) from kernel tests.
Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
The test assumes that the last to IRQ numbers will be free, this isn't a
valid assumption and now that we detect multiple ISRs registering for
the some IRQ line, we see failures because of this assumption on some
platforms. Exclude those platforms from this test for the time being.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a new test and we have riscv32 failing on that all of the
sudden. Disabling while we look into it and identify if that is a
testcase issue or not.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This test is intended to verify the interrupt nesting.
Interrupt nesting feature allows an ISR to be preempted
in mid-execution if a higher priority interrupt is signaled.
The lower priority ISR resumes execution once the higher
priority ISR has completed its processing.
Signed-off-by: Ajay Kishore <ajay.kishore@intel.com>
