Change the CPU_CORTEX_R kconfig option to CPU_AARCH32_CORTEX_R to
distinguish the armv7 version from the armv8 version of Cortex-R.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
The irq_lock() API is a legacy API not to be used for synchronization
by new code, and in any case is only being used in cargo-cult fashion
here. These test cases all do synchronous exceptions, there's
literally nothing to synchronize against.
(And in this case they're exposing a legacy wart. On platforms where:
1. SMP=y, which causes irq_lock() to be implemented as a somewhat
complicated global lock
2. No ARCH_EXCEPT() macro is defined, which causes the kernel to
use a fallback that simply aborts the current thread.
...this test will then abort a thread holding the lock, which will
cause it to be orphaned (if it weren't a legacy API, the kernel
should probably attempt to clean it up in k_thread_abort(), but it
is, and it doesn't), so the next attempt to lock it will hang.
And it's even worse, because this test builds with SMP=y and
MP_NUM_CPUS=1, so the hand will happen with interrupts masked on a
system with only one CPU, and everything will lock up solid.)
Fixes#41877
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
We don't use TLB at the moment. Jumping to address 0 (USEG)
leads to TLB exception (instruction fetch).
Division by zero leads to TRAP exception.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Currently a test is failing.
```
twister -i -p qemu_cortex_a9 \
-s tests/kernel/fatal/exception/kernel.common.stack_sentinel
```
Disable those temporarily until a fix is in place.
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Add consideration of aarch32 Cortex-A CPUs to a test case in which
architecture-specific assembly instructions are used in order to
explicitly trigger an exception. This test case already considers
aarch32 Cortex-R CPUs, the same instruction will be used by
Cortex-A CPUs.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
For hardware stack overflow test, pin the whole stack if
demand paging is enabled and generic sections are not all present
at boot. The whole stack may not be in memory at the time of
test, which would result in double fault (exception being
handled + page fault). So make sure the stack is in physical
memory and mapped before doing any tests.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move to CMake 3.20.0.
At the Toolchain WG it was decided to move to CMake 3.20.0.
The main reason for increasing CMake version is better toolchain
support.
Better toolchain support is added in the following CMake versions:
- armclang, CMake 3.15
- Intel oneAPI, CMake 3.20
- IAR, CMake 3.15 and 3.20
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Introduce the fpu tag to tests that explicitly enable
the FPU and FPU_SHARING Kconfig options. The tag could
be used to run all FPU-related tests in the tree.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This test takes an interrupt lock and tries to call z_swap_unlocked()
while holding it. That's not legal (in the general case it means
you're breaking a caller's lock!), though in this particular case it
was safe because we'll never return to this.
Regardless, there is a natural z_swap_irqlock() that releases the lock
atomically. Use that.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Improve the test case of CPU exception.
Add equivalence classes and input partition testing
when give an integer reason code.
Signed-off-by: Ying ming <mingx.ying@intel.com>
The "sentinel" variant of this test runs the same code, but enables
the stack sentinel feature. Inexplicably, it's also disabling
TICKLESS_KERNEL, forcing a timer interrupt at every tick boundary.
That doesn't seem to be required for any test functionality I can see.
And worse, by changing that setting without adjusting the tick rate,
it runs afoul of more modern platforms which were designed with
tickless operation in mind. Specifically, the intel_adsp platforms
have a default tick rate of 50 kHz, which is just too fast for
reasonable operation. It leaves almost no time available for
application code and something falls behind and fails.
Just remove it.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Use of a printk that supports floating point changes the stack
requirements causing kernel.common.stack_protection_arm_fpu_sharing to
fail. The test doesn't need this capability so revert to nano
formatting.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The memset in the 'blow_up_stack' function can be optimized
away as it is called in the end of the function on the buffer
allocated on the stack (so it has 'no' effect on program
execution)
The 'stack_smasher' call can be optimized away as it's results
isn't used anywhere and stack_smasher function has no visible
side effects.
Fix that by disabling optimization on these functions.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Some ARM platforms, now, enable HW Stack Protection by
default in the Board definition. So if some tests
need to run without stack protection, it is not
sufficient to disable TEST_HW_STACK_PROTECTION;
we need to explicitly disable HW_STACK_PROTECTION.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
- They all had the wrong prototype and hard-casts can sometimes
lead to problems
- Several renamed to something more descriptive
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Modify the location of the test case file because new
test cases need to be submitted. If the old test
cases are not in a folder, CI will fail and
prompts "the command exited with status 1".
Signed-off-by: Ying ming <mingx.ying@intel.com>
