We emulate the interrupt by sending the IPI to core itself by
the local APIC for x86 platfrom.
But in X2APIC mode, this no longer works. So we emulate the
interrupt the by writing the IA32_X2APIC_SELF_IPI MSR to send
IPI to the core itself via LOAPIC also. According to SDM vol.3
chapter 10.12.11.
Fixes#42108
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
MIPS (Microprocessor without Interlocked Pipelined Stages) is a
instruction set architecture (ISA) developed by MIPS Computer
Systems, now MIPS Technologies.
This commit provides MIPS architecture support to Zephyr. It is
compatible with the MIPS32 Release 1 specification.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
For x86, make the testing purpose trigger_irq() function to send
interrupt processor interrupt to CPU by APIC, instead of executing
INT instruction. Doing this because:
1. It can be controlled by irq lock, more close to trigger irq.
2. We don't need to hardcode the interrupt vector.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
The interrupt_util.h provides utils of trigger irq, now move them into
testsuite. All of the needed test cases can make use of them.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
