This is required by drivers which query the current cpu,
at this moment there is no arm aarch32 that use smp,
so it seems safe to consider that the current cpu is
always the first one.
This patch enable the use of the GICv3 driver on
ARM 32bits cpu.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
These definitions are required to be able to use GICv3
interrupts controller on an ARMv8 AArch32 processor.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This is mostly a copy of the existing arm64 implementation,
at the difference that the AArch32 registers do not mention the
execution level.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
lib_helpers makes easier to access cp15 based registers,
it is inspired from arm64 lib_helpers but use
MRC instead of MRS and use cp15 register.
Definitions on how to access system registers for AArch32
Armv8 processors can be found in the document:
Arm Architecture Reference Manual Armv8,
for Armv8-A architecture profile
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The ARMv8-R processors always boot into Hyp mode (EL2)
To enter EL1:
Program the HACTLR register because it defaults
to only allowing EL2 accesses. HACTLR controls
whether EL1 can access memory region registers and CPUACTLR.
Program the SPSR before entering EL1.
Other registers default to allowing accesses at EL1 from reset.
Set VBAR to the correct location for the vector table.
Set ELR to point to the entry point of the EL1 code and call ERET.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
In the Armv8R AArch64 profile[1], the Armv8R AArch64 is always in secure
mode. But the FVP_BaseR_AEMv8R before version 11.16.16 doesn't strictly
follow this rule. It still has some non-secure registers
(e.g. CNTHP_CTL_EL2).
Since version 11.16.16, the FVP_BaseR_AEMv8R has fixed this issue. The
CNTHP_XXX_EL2 registers have been changed to CNTHPS_XXX_EL2. So the
FVP_BaseR_AEMv8R (version >= 11.16.16) cannot boot Zephyr. This patch
will fix it.
[1] https://developer.arm.com/documentation/ddi0600/latest/
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: If986f34dc080ae7a8b226bba589b6fe616a4260b
It turns out XCC didn't like this change as it doesn't have a
__COUNTER__ builtin. Bummer.
This reverts commit e8389f2f53.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Change the CPU_CORTEX_R kconfig option to CPU_AARCH32_CORTEX_R to
distinguish the armv7 version from the armv8 version of Cortex-R.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Depending on whether X2APIC is enabled or not, it will be safer to grab
such ID from the right place.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will centralize CPUID related accessors. There was no need for it
so far, but this is going to change.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Introduce a new "zephyr,memory-region" compatible to be used when a new
memory region must be created in the linker script from the devicetree
nodes using the compatible.
Remove also the LINKER_DT_REGION_FROM_NODE macro and add a new
LINKER_DT_REGIONS macro to cycle through all the compatible regions.
In the same PR modify the DTS files and the linker scripts.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This align the RISC-V linker script with ARM linker script.
(The snippets-ram-sections.ld is included first inside the
RAMABLE_REGION)
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Makes the IRQ_CONNECT macro statically declarable for Xtensa (nothing
prevented it except its structuring). Allows for IRQ_CONNECT usage
on a xtensa only platform to be declared statically avoiding the
fluff of setting up and enabling irqs for cavs gpdma.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
These functions help the code to be more self-documenting. Use them to
make the code's intent clearer.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
MIPS (Microprocessor without Interlocked Pipelined Stages) is a
instruction set architecture (ISA) developed by MIPS Computer
Systems, now MIPS Technologies.
This commit provides MIPS architecture support to Zephyr. It is
compatible with the MIPS32 Release 1 specification.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Currently, is_user_mode is 8-byte in riscv64 and it breaks a 4-byte PMP
region protecting it. Because is_user_mode is a single flag, we could
just fix it's size to 4-byte in both riscv32 and riscv64.
Signed-off-by: Jim Shu <cwshu09@gmail.com>
In RV64, all general-purpose registers and pmpcfg CSR are 64-bit
instead of 32-bit. Fix these registers and related C variables/literals
to be 32/64-bit compatible.
Signed-off-by: Jim Shu <cwshu09@gmail.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is trick (mapping RAM twice so you can use alternate Region
Protection Option addresses to control cacheability) is something any
Xtensa hardware designer might productively choose to do. And as it
works really well, we should encourage that by making this a generic
architecture feature for Zephyr.
Now everything works by setting two kconfig values at the soc level
defining the cached and uncached regions. As long as these are
correct, you can then use the new arch_xtensa_un/cached_ptr() APIs to
convert between them and a ARCH_XTENSA_SET_RPO_TLB() macro that
provides much smaller initialization code (in C!) than the HAL
assembly macros. The conversion routines have been generalized to
support conversion between any two regions.
Note that full KERNEL_COHERENCE still requires support from the
platform linker script, that can't be made generic given the way
Zephyr does linkage.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The header contains macros that make use of the Devicetree API, however,
<devicetree.h> is not included. This was "mitigated" by most <soc.h>
including <devicetree.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Simplify multiple ifdef case in computing region number. Also move these
macros to core_pmp.c because they are only used in one file.
Signed-off-by: Jim Shu <cwshu@andestech.com>
_image_ram_start symbol is duplicate in CONFIG_USERSPACE. This symbol
should be at the start of app_smem in userspace, so remove another
symbol in CONFIG_USERSPACE.
Signed-off-by: Jim Shu <cwshu@andestech.com>
The function `zephyr_linker_sources()` states:
> When placing into NOINIT, RWDATA, RODATA, ROM_START, the contents of
> the files will be placed inside an output section, so assume the
> section definition is already present.
However, in the posix linker.ld template the NOINIT, RWDATA, RODATA, and
ROM_START was not placed inside a pre-defined output section, which
means that linker scripts created for native_posix when
`zephyr_linker_sources()` is used are invalid
This result in the following failure:
> /usr/bin/ld:zephyr/linker_zephyr_prebuilt.cmd:81: syntax error
> collect2: error: ld returned 1 exit status
This PR fixes this issue be predefining output sections according to
the documented behavior.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Depending on a VT-D capability, it might be necessary to flush objects
from the cache.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Looks like it's mandatory to invalidate the Interrupt Entry Cache in
VT-D and the only way to do so is to enable Queued Interface.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
IR faults are non-recoverable, so it's good to know why. Thus let's
handle the fault event and print the fault.
Other faults are printed as well.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
While this does not change anything for ia32, this is fixing the chicken
& egg issue on intel64 if (and only if) interrupt remapping is enabled
so pcie_connect_dynamic_irq() is to be called properly.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Fix for issue 39978. This commit assigns the __rodata_region_start marker
to the ROMABLE region prior to the inclusion of linker/common-rom.ld,
linker/thread-local-storage.ld and linker/cplusplus-rom.ld. Prior to this
fix, the __rodata_region_start marker was properly aligned and indicated
the expected memory location for the start of the rodata section and
similar sections, but it was disconnected from the ROMABLE region into
which the subsequent sections are being integrated, resulting in placement
of those sections right behind the previous section in the ROMABLE region
and therefore at addresses below the __rodata_region_start marker.
For the sake of consistent behaviour, the end marker of the text region
has been modified accordingly.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Fix the mapping of the sections to be located in the On-Chip
Memory so that the OCM memory region name always matches that
of the chosen OCM DT node's memory-region attribute.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Enable ARCH_EXCEPT macro for non-usermode scenario for RISC-V
Macro will now raise an illegal instruction exception so that mepc will
hold expected value in exception handler, and generated coredump can
reconstruct the failing stack
Coredump tests running on renode (for RISC-V) can now utilize fatal error
path through k_panic
Signed-off-by: Mark Holden <mholden@fb.com>
The commit a28830b aligned the data and rename some symbols. However
there are two symbols at riscv linker script that were missing, which
causes below linker error:
kernel/xip.c:28: undefined reference to `__itcm_load_start'
kernel/xip.c:43: undefined reference to `__dtcm_data_load_start'
Rename below symbols to fix the issues.
__itcm_rom_start -> __itcm_load_start
__dtcm_data_rom_start -> __dtcm_data_load_start
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This file started using ALWAYS_INLINE from <toolchain.h> but didn't
include it. Transitive inclusions were hiding the problem most
places, but at least one test case exposes it.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These are tiny functions always declared as "inline" per C99, but
that's just a hint. In practice, they tend to be (c.f. intel_asdp)
called from very early boot circumstances where main application
symbols aren't yet available. That obviously doesn't work, or even
link.
Make them ALWAYS_INLINE. In practice they're so small that we don't
want them called anyway just for stack space reasons.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
As memory region names are now derived purely from devicetree, remove
the `name` parameter from `DT_REGION_FROM_NODE_STATUS_OKAY`. Name is
`zephyr,linker-region` if it exists, otherwise the node path.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This adds basic support for GDB stub on Xtensa. Note that
this only provides the common bits on the architecture side.
SoC support is also required to fully enable GDB stub on
each Xtensa SoC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds some architecture-specific functions to read/write
registers for the GDB stub. This is in preparation for the actual
introduction of these functions in the core GDB stub code to
avoid breaking the build in between commits.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The RISC-V architecture linker script was including `cplusplus-ram.ld`
linker script before `__data_region_start`, and this caused the content
of `.gcc_except_table` section to be not copied to the RAM by the
`z_data_copy` function; leading to the C++ exception handling
malfunction.
This commit relocates the `cplusplus-ram.ld` linker script inclusion
such that the contents of the relevant sections are properly copied by
the `z_data_copy` function.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
