Strictly speaking not a problem for in-tree tooling, but better to
have all binding files follow the same naming convention.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Introduce DeviceTree binding for the STM32MP2 RCC clock controller,
enabling support for STM32MP2-specific clock configuration in Zephyr.
Update Kconfig.stm32 to add a dependency on STM32MP2 configuration,
allowing the use of STM32 LL RCC features when targeting STM32MP2
devices.
Add header for STM32MP2 per peripheral clock definitions.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Current ESP32 clock system is mixed with RTC labeling/registers,
but it doesn't implement a real-time clock (RTC) driver.
To avoid confusion and allow adding a proper RTC driver later,
this commit renames the existing RTC interface to CLOCK and make
it as a subsystem without any peripheral attached to it.
This better reflects its actual purpose as a general clock controller.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the clock startup time property to the nrf54l series HFXO binding.
Note that the values added to the soc .dtsi files are worst case
defaults, which will be replaced with optimal values at board level
in the future, as they depend on the specific crystal in use.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Each nrf series has its own variant of the lfxo clock, specified
by the binding which includes the series in the name. The nrf54L
series is no different, hence the binding should be clearly
specified by having the series name within it.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Each nrf series has its own variant of the hfxo clock, specified
by the binding which includes the series in the name. The nrf54L
series is no different, hence the binding should be clearly
specified by having the series name within it.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add the clock startup time property to the nrf53 series HFXO binding.
Note that the values added to the soc .dtsi files are worst case
defaults, which will be replaced with optimal values at board level
in the future, as they depend on the specific crystal in use.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add nrf52 series hfxo binding and nodes to socs.
Note that the values added to the soc .dtsi files are worst case
defaults, which will be replaced with optimal values at board level
in the future, as they depend on the specific crystal in use.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add nrf51 series hfxo binding and nodes to socs.
Note that the values added to the soc .dtsi files are worst case
defaults, which will be replaced with optimal values at board level
in the future, as they depend on the specific crystal in use.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Remove the closed loop mode implementation for the fll16m clock.
Closed loop causes a hardware bug resulting in increased current
consumption if SoC experiences high, but within spec, temperatures.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This adds a proper, concise, title property to a bunch of bindings for
which the first sentence of their description (which used to be a
makeshift title) was really long
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Rename the frac-v PLL binding into fracn in order to make it
consistent with other STM32 PLL bindings.
This commit also correct the range which should be 0 - 8191.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Depending on the PLL, all DIV-P / DIV-Q and DIV-R are available
on STM32MP13 PLLs.
Adjust valid range in order to be able to set for all 4 PLLs.
Clarify DT properties description.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Initial support of clock control driver for RX MCU
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
Clean up dt binding descriptions and introduce titles where
needed to make board documentation pages look nice. The supported
hardware table on board documentation pages sources its data
from dt bindings, and needs succinct titles.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add clock control support for RZ/A2M
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
Errata sheet ES0620 indicates that STM32N6 APB prescalers cannot be
modified.
Fixes the value of all APB prescalers to 1 (default value).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add Clock Control driver support for Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Rename the following properties in bindings and DTS:
-- freqs_mhz => freqs-mhz
-- cg_reg => cg-reg
-- pll_ctrl_reg => pll-ctrl-reg
Signed-off-by: James Roy <rruuaanng@outlook.com>
This driver is mostly the initial seed for further implementation of a
real clock driver.
It doesn't allow the user to choose the clock source for the various
peripherals. The driver hardcodes some sane values.
Note that for now, the driver snps,designware-i2c does not support
"clocks" attribute. So this patch hardcode the clock configuration in
the init of the clock driver.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The Atmel SAM0 SoC enable peripherals clocks in distinct places: PM and
MCLK. The old devices had defined the peripheral clock enable bit at PM.
On the newer devices this was extracted on a dedicated memory section
called Master Clock (MCLK). This change excludes the dedicated bindings
in favor of a generic approach that cover all cases.
Now the clocks properties is complemented by the atmel,assigned-clocks
property. It gives the liberty to user to customize the clock source
from a generic clock or configure the direct connections.
All peripherals drivers were reworked with the newer solution.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some platforms require special clock selection options. This could be
made using the already defined assigned-clocks from Linux clocks.
See 93ee800895/dtschema/schemas/clock/clock.yaml (L24)
This introduces the vendor atmel,assigned-clocks and
atmel,assigned-clock-names properties to generalize those conditions
in Zephyr for Atmel sam0 SoC series.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The nrf-hsfll was previously the only supported HSFLL clock, hence it
was not namespaced fully. Since we added nrf-hsfll-global, we should
add the namespace to nrf-hsfll as well.
Updates drivers and devicetree uses of HSFLL as well.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add specific device model for global hsfll clock and update dts tree
to use specific model. The clock is not fixed, and configurable at
runtime to predefined frequencies specified by the platform.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Support specifying divided clock buses by introduction of
STM32_CLOCK_DIV(div) macro. This macro can be used in devicetree to define
clock source of peripherals.
HSE is selected in devicetree using:
<&rcc STM32_SRC_HSE ...>;
HSE/2 can now be selected with:
<&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) ...>;
This allows to use clock_control_get_rate() API in peripherals in order to
get desired clock rate.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Depending on the stm32 serie the MCO1/2 prescaler is a value
set in the CFGR register to divide the MCO output clock.
Use the same model based on the RefMan for other stm32 series
than stm32C0/F4/F7/H5/H7, once the MCO is in the DTS.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
