On Cortex-M33 the access to peripheral registers doesn't act as a data
synchronization barrier for memory accesses to normal memory. So before
triggering any TASKS for cache operations we need to make sure the core
doesn't have any pending memory transactions.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Apply changes which significantly speed up cache operations.
Removed k_busy_wait from function which polls for cache busyness.
Removed spinlock from cache operation. Lock taking and releasing
takes time and it is faster to check if LINEADDR changed
after performing the operation. If LINEADDR changed then it
indicates that current context was preempted by another cache
operation. If such state is detected current operation is
repeated.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Driver was disabling cache before full range operations and that
was causing hanging on polling for cache busy status since
state was never changing (because cache was disabled).
Additionally, added flushing to data cache disabling. If flushing
is not performed then execution fails since data in cache is lost.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
nrf54h20 has a bug that requires to manually set 28th bit in the line
address. 28th bit indicates secure memory space. Add handling to the
cache driver.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
