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clock_control: fix to get PLL2 source for PREDV1 working

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Some fixes where needed to get PLL2 source of PREVI1 functional.
Compiled ok with following configuration:
CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK=y
CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2=0
CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER=8

Jira: ZEP-1758

Change-Id: I5ddfaef1b44c4c4e5e6adedc158a1c9092bc8df5
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2017-02-20 10:39:55 +01:00 committed by Kumar Gala
parent 0aea704462
commit de684bbdaa
1 changed files with 10 additions and 3 deletions
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13
drivers/clock_control/stm32f107xx_clock.c
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@ -286,8 +286,8 @@ static int stm32f10x_clock_control_init(struct device *dev)
pllmul(CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER);
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER
uint32_t pll2mul =
pllmul(CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER);
uint32_t pll2_mul =
pll2mul(CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER);
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1
uint32_t prediv1 =
@ -341,7 +341,14 @@ static int stm32f10x_clock_control_init(struct device *dev)
rcc->cfgr2.bit.prediv1src = STM32F10X_RCC_CFG2_PREDIV1_SRC_PLL2;
rcc->cfgr2.bit.prediv2 = prediv2;
rcc->cfgr2.bit.pll2mul = pll2mul;
rcc->cfgr2.bit.pll2mul = pll2_mul;
/* enable PLL2 */
rcc->cr.bit.pll2on = 1;
/* wait for PLL to become ready */
while (rcc->cr.bit.pll2rdy != 1) {
}
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE */
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1 */