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xtensa: no need to restore A0/A1 if not coherence in irq exit

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Towards the end of interrupt handling, and before restoring
context, we would spill all register windows. This requires
A0 and A1 to be restored from the saved context so spilling
would work correct. However, when coherence is enabled,
window spilling has already been done earlier so there is
no need to spill the register windows again. So there is
no need to restore A0 and A1. They will be restored again
before returning from interrupt anyway.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2025-04-03 15:25:38 -07:00 committed by Benjamin Cabé
parent 0dce0bdc0b
commit 9ebe16b6e7
1 changed files with 3 additions and 2 deletions
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5
arch/xtensa/include/xtensa_asm2_s.h
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@ -520,11 +520,12 @@ _do_call_\@:
*/
beq a6, a1, _restore_\@
#if !defined(CONFIG_KERNEL_COHERENCE) || \
(defined(CONFIG_KERNEL_COHERENCE) && defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY))
l32i a1, a1, 0
l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF
#if !defined(CONFIG_KERNEL_COHERENCE) || \
(defined(CONFIG_KERNEL_COHERENCE) && defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY))
/* When using coherence, the registers of the interrupted
* context got spilled upstream in arch_cohere_stacks()
*/