From 9ebe16b6e7811e543138696ea2ad50cb7bd5676a Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Thu, 3 Apr 2025 15:25:38 -0700 Subject: [PATCH] xtensa: no need to restore A0/A1 if not coherence in irq exit Towards the end of interrupt handling, and before restoring context, we would spill all register windows. This requires A0 and A1 to be restored from the saved context so spilling would work correct. However, when coherence is enabled, window spilling has already been done earlier so there is no need to spill the register windows again. So there is no need to restore A0 and A1. They will be restored again before returning from interrupt anyway. Signed-off-by: Daniel Leung --- arch/xtensa/include/xtensa_asm2_s.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/include/xtensa_asm2_s.h b/arch/xtensa/include/xtensa_asm2_s.h index bc6d212bd15..8115c6f6869 100644 --- a/arch/xtensa/include/xtensa_asm2_s.h +++ b/arch/xtensa/include/xtensa_asm2_s.h @@ -520,11 +520,12 @@ _do_call_\@: */ beq a6, a1, _restore_\@ +#if !defined(CONFIG_KERNEL_COHERENCE) || \ + (defined(CONFIG_KERNEL_COHERENCE) && defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY)) l32i a1, a1, 0 l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF -#if !defined(CONFIG_KERNEL_COHERENCE) || \ - (defined(CONFIG_KERNEL_COHERENCE) && defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY)) + /* When using coherence, the registers of the interrupted * context got spilled upstream in arch_cohere_stacks() */