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soc/intel_asdp: Unify misc. initialization registers

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These two register blocks are defined in the platform layers, but
never change (except on 1.5 where they don't exist).  I don't want to
write a full devicetree interface for them as I can't find good docs
currently.  They are used only at system initialization, so move the
definitions to the single file where they're used.  In the longer term
we will want to move at least the GPDMA setup into a driver anyway.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-10-20 11:08:46 -07:00 committed by Anas Nashif
parent cb73032a32
commit 9cba8501df
4 changed files with 15 additions and 51 deletions
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17
soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h
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@ -15,21 +15,4 @@
#define IRQ_CPU_OFFSET 0x40
/** \brief GPDMA shim registers Control */
#define SHIM_GPDMA_BASE_OFFSET 0x6500
#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
/** \brief GPDMA Clock Control */
#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
#define LPGPDMA_CTLOSEL_FLAG BIT(15)
#define LPGPDMA_CHOSEL_FLAG 0xFF
#define DSP_INIT_GENO 0x71A6C
#define GENO_MDIVOSEL BIT(1)
#define GENO_DIOPTOSEL BIT(2)
#endif /* __PLATFORM_LIB_SHIM_H__ */

17
soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h
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@ -15,21 +15,4 @@
#define IRQ_CPU_OFFSET 0x40
/** \brief GPDMA shim registers Control */
#define SHIM_GPDMA_BASE_OFFSET 0x6500
#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
/** \brief GPDMA Clock Control */
#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
#define LPGPDMA_CTLOSEL_FLAG BIT(15)
#define LPGPDMA_CHOSEL_FLAG 0xFF
#define DSP_INIT_GENO 0x71A6C
#define GENO_MDIVOSEL BIT(1)
#define GENO_DIOPTOSEL BIT(2)
#endif /* __PLATFORM_LIB_SHIM_H__ */

17
soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h
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@ -15,21 +15,4 @@
#define IRQ_CPU_OFFSET 0x40
/** \brief GPDMA shim registers Control */
#define SHIM_GPDMA_BASE_OFFSET 0x6500
#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
/** \brief GPDMA Clock Control */
#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
#define LPGPDMA_CTLOSEL_FLAG BIT(15)
#define LPGPDMA_CHOSEL_FLAG 0xFF
#define DSP_INIT_GENO 0x71A6C
#define GENO_MDIVOSEL BIT(1)
#define GENO_DIOPTOSEL BIT(2)
#endif /* __PLATFORM_LIB_SHIM_H__ */

15
soc/xtensa/intel_adsp/common/soc.c
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@ -23,6 +23,21 @@
#include <logging/log.h>
LOG_MODULE_REGISTER(soc);
#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15
# define SHIM_GPDMA_BASE_OFFSET 0x6500
# define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
# define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
# define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
# define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
# define LPGPDMA_CTLOSEL_FLAG BIT(15)
# define LPGPDMA_CHOSEL_FLAG 0xFF
# define DSP_INIT_GENO 0x71A6C
# define GENO_MDIVOSEL BIT(1)
# define GENO_DIOPTOSEL BIT(2)
#endif
#define CAVS_INTC_NODE(n) DT_INST(n, intel_cavs_intc)
void z_soc_irq_enable(uint32_t irq)