diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h
index 82d393b19e1..312cb921d23 100644
--- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h
+++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h
@@ -15,21 +15,4 @@
 
 #define IRQ_CPU_OFFSET	0x40
 
-/** \brief GPDMA shim registers Control */
-#define SHIM_GPDMA_BASE_OFFSET	0x6500
-#define SHIM_GPDMA_BASE(x)	(SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
-
-/** \brief GPDMA Clock Control */
-#define SHIM_GPDMA_CLKCTL(x)	(SHIM_GPDMA_BASE(x) + 0x4)
-/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
-#define SHIM_CLKCTL_LPGPDMAFDCGB	BIT(0)
-
-#define DSP_INIT_LPGPDMA(x)	(0x71A60 + (2*x))
-#define LPGPDMA_CTLOSEL_FLAG	BIT(15)
-#define LPGPDMA_CHOSEL_FLAG	0xFF
-
-#define DSP_INIT_GENO	0x71A6C
-#define GENO_MDIVOSEL		BIT(1)
-#define GENO_DIOPTOSEL		BIT(2)
-
 #endif /* __PLATFORM_LIB_SHIM_H__ */
diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h
index 82d393b19e1..312cb921d23 100644
--- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h
+++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h
@@ -15,21 +15,4 @@
 
 #define IRQ_CPU_OFFSET	0x40
 
-/** \brief GPDMA shim registers Control */
-#define SHIM_GPDMA_BASE_OFFSET	0x6500
-#define SHIM_GPDMA_BASE(x)	(SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
-
-/** \brief GPDMA Clock Control */
-#define SHIM_GPDMA_CLKCTL(x)	(SHIM_GPDMA_BASE(x) + 0x4)
-/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
-#define SHIM_CLKCTL_LPGPDMAFDCGB	BIT(0)
-
-#define DSP_INIT_LPGPDMA(x)	(0x71A60 + (2*x))
-#define LPGPDMA_CTLOSEL_FLAG	BIT(15)
-#define LPGPDMA_CHOSEL_FLAG	0xFF
-
-#define DSP_INIT_GENO	0x71A6C
-#define GENO_MDIVOSEL		BIT(1)
-#define GENO_DIOPTOSEL		BIT(2)
-
 #endif /* __PLATFORM_LIB_SHIM_H__ */
diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h
index 69c44f83572..312cb921d23 100644
--- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h
+++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h
@@ -15,21 +15,4 @@
 
 #define IRQ_CPU_OFFSET	0x40
 
-/** \brief GPDMA shim registers Control */
-#define SHIM_GPDMA_BASE_OFFSET 0x6500
-#define SHIM_GPDMA_BASE(x)     (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
-
-/** \brief GPDMA Clock Control */
-#define SHIM_GPDMA_CLKCTL(x)   (SHIM_GPDMA_BASE(x) + 0x4)
-/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
-#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
-
-#define DSP_INIT_LPGPDMA(x)	(0x71A60 + (2*x))
-#define LPGPDMA_CTLOSEL_FLAG	BIT(15)
-#define LPGPDMA_CHOSEL_FLAG	0xFF
-
-#define DSP_INIT_GENO	0x71A6C
-#define GENO_MDIVOSEL		BIT(1)
-#define GENO_DIOPTOSEL		BIT(2)
-
 #endif /* __PLATFORM_LIB_SHIM_H__ */
diff --git a/soc/xtensa/intel_adsp/common/soc.c b/soc/xtensa/intel_adsp/common/soc.c
index e0e80f045ea..9650eeafd62 100644
--- a/soc/xtensa/intel_adsp/common/soc.c
+++ b/soc/xtensa/intel_adsp/common/soc.c
@@ -23,6 +23,21 @@
 #include <logging/log.h>
 LOG_MODULE_REGISTER(soc);
 
+#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15
+# define SHIM_GPDMA_BASE_OFFSET   0x6500
+# define SHIM_GPDMA_BASE(x)       (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
+# define SHIM_GPDMA_CLKCTL(x)     (SHIM_GPDMA_BASE(x) + 0x4)
+# define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
+
+# define DSP_INIT_LPGPDMA(x)	  (0x71A60 + (2*x))
+# define LPGPDMA_CTLOSEL_FLAG	  BIT(15)
+# define LPGPDMA_CHOSEL_FLAG	  0xFF
+
+# define DSP_INIT_GENO	          0x71A6C
+# define GENO_MDIVOSEL		  BIT(1)
+# define GENO_DIOPTOSEL           BIT(2)
+#endif
+
 #define CAVS_INTC_NODE(n) DT_INST(n, intel_cavs_intc)
 
 void z_soc_irq_enable(uint32_t irq)