arch: arm: cortex_a_r: Flush entire I-cache on arch_icache_invd_range

Previously, the arch_icache_invd_range function simply returned
-ENOTSUP for Cortex A/R. However, this causes a correctness issue when
the processor modifies memory and then executes it as instructions, like
the LLEXT subsystem does. The CPU might not see the up-to-date instructions
in memory.

This caused an LLEXT test failure when running on an emulated Cortex-R5
in QEMU with caches enabled. QEMU doesn't actually emulate the cache,
but it does seem to need the ISB barrier that is executed as part of the
cache invalidate operation in order to handle self-modifying code
properly.

These CPUs do in fact support a selective I-cache invalidate operation
(ICIMVAU) but the CMSIS library doesn't currently support it. For now,
just invalidate the entire I-cache when an icache_invd_range operation
is performed.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>

arch/arm/core/cortex_a_r/cache.c

@@ -208,7 +208,13 @@ int arch_icache_flush_range(void *start_addr, size_t size)
 
 int arch_icache_invd_range(void *start_addr, size_t size)
 {
-	return -ENOTSUP;
+	/* Cortex A/R do have the ICIMVAU operation to selectively invalidate
+	 * the instruction cache, but not currently supported by CMSIS.
+	 * For now, invalidate the entire cache.
+	 */
+	L1C_InvalidateICacheAll();
+
+	return 0;
 }
 
 int arch_icache_flush_and_invd_range(void *start_addr, size_t size)