diff --git a/arch/arm/core/cortex_a_r/cache.c b/arch/arm/core/cortex_a_r/cache.c
index 31cf27a08e6..07c5b32bf32 100644
--- a/arch/arm/core/cortex_a_r/cache.c
+++ b/arch/arm/core/cortex_a_r/cache.c
@@ -208,7 +208,13 @@ int arch_icache_flush_range(void *start_addr, size_t size)
 
 int arch_icache_invd_range(void *start_addr, size_t size)
 {
-	return -ENOTSUP;
+	/* Cortex A/R do have the ICIMVAU operation to selectively invalidate
+	 * the instruction cache, but not currently supported by CMSIS.
+	 * For now, invalidate the entire cache.
+	 */
+	L1C_InvalidateICacheAll();
+
+	return 0;
 }
 
 int arch_icache_flush_and_invd_range(void *start_addr, size_t size)