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soc/riscv32-fe310: Enable DTS gen for SPI

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Add the SPI bus DTS generation to the FE310 and the SiFive Freedom SoC.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
This commit is contained in:
Nathaniel Graff 2018-11-21 11:30:29 -08:00 committed by Kumar Gala
parent 9e2ef8db6d
commit 596e44d244
1 changed files with 3 additions and 0 deletions
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3
dts/riscv32/riscv32-fe310.dtsi
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@ -170,6 +170,7 @@
interrupts = <5>;
reg = <0x10014000 0x1000 0x20000000 0x20000000>;
reg-names = "control", "mem";
label = "spi_0";
status = "disabled";
};
spi1: spi@10024000 {
@ -178,6 +179,7 @@
interrupts = <6>;
reg = <0x10024000 0x1000>;
reg-names = "control";
label = "spi_1";
status = "disabled";
};
spi2: spi@10034000 {
@ -186,6 +188,7 @@
interrupts = <7>;
reg = <0x10034000 0x1000>;
reg-names = "control";
label = "spi_2";
status = "disabled";
};
teststatus: teststatus@4000 {