From 596e44d244cdb9dc317a9e7193bfbb6d459eed7b Mon Sep 17 00:00:00 2001
From: Nathaniel Graff <nathaniel.graff@sifive.com>
Date: Wed, 21 Nov 2018 11:30:29 -0800
Subject: [PATCH] soc/riscv32-fe310: Enable DTS gen for SPI

Add the SPI bus DTS generation to the FE310 and the SiFive Freedom SoC.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
---
 dts/riscv32/riscv32-fe310.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/dts/riscv32/riscv32-fe310.dtsi b/dts/riscv32/riscv32-fe310.dtsi
index adf96cdefd5..deb4a8ae5b0 100644
--- a/dts/riscv32/riscv32-fe310.dtsi
+++ b/dts/riscv32/riscv32-fe310.dtsi
@@ -170,6 +170,7 @@
 			interrupts = <5>;
 			reg = <0x10014000 0x1000 0x20000000 0x20000000>;
 			reg-names = "control", "mem";
+			label = "spi_0";
 			status = "disabled";
 		};
 		spi1: spi@10024000 {
@@ -178,6 +179,7 @@
 			interrupts = <6>;
 			reg = <0x10024000 0x1000>;
 			reg-names = "control";
+			label = "spi_1";
 			status = "disabled";
 		};
 		spi2: spi@10034000 {
@@ -186,6 +188,7 @@
 			interrupts = <7>;
 			reg = <0x10034000 0x1000>;
 			reg-names = "control";
+			label = "spi_2";
 			status = "disabled";
 		};
 		teststatus: teststatus@4000 {