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drivers: gpio: Add support for RZ/V2N

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Add support for RZ/V2N

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
This commit is contained in:
Tien Nguyen 2025-06-10 10:14:48 +07:00 committed by Daniel DeGrasse
parent 05289f40a7
commit 5599bc2ecb
3 changed files with 128 additions and 3 deletions
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2
drivers/gpio/gpio_renesas_rz.c
View File

@ -352,7 +352,7 @@ static int gpio_rz_int_enable(const struct device *gpio_int_dev, const struct de
/* Select interrupt source base on port and pin number. */
*tssr &= ~(0xFF << (int_num));
*tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(int_num);
/* Select TINT source(only for RZV2H) */
/* Select TINT source */
GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR(int_num);
GPIO_RZ_TINT_SELECT_SOURCE_REG_SET(int_num);

5
drivers/gpio/gpio_renesas_rz.h
View File

@ -14,7 +14,8 @@
#if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL) || \
defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L) || \
defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZG2UL)
defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZG2UL) || \
defined(CONFIG_SOC_SERIES_RZV2N)
#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
#if defined(CONFIG_SOC_SERIES_RZG3S)
@ -39,7 +40,7 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43,
47, 52, 56, 58, 63, 66, 70, 72, 76};
#elif defined(CONFIG_SOC_SERIES_RZV2H)
#elif defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZV2N)
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P20)
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM20)
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC20)

124
dts/arm/renesas/rz/rzv/r9a09g056.dtsi
View File

@ -36,6 +36,130 @@
compatible = "renesas,rzv-pinctrl";
reg = <0x40410000 DT_SIZE_K(64)>;
reg-names = "pinctrl";
gpio: gpio-common {
compatible = "renesas,rz-gpio-int";
interrupts =
<353 10>, <354 10>, <355 10>, <356 10>,
<357 10>, <358 10>, <359 10>, <360 10>,
<361 10>, <362 10>, <363 10>, <364 10>,
<365 10>, <366 10>, <367 10>, <368 10>,
<369 10>, <370 10>, <371 10>, <372 10>,
<373 10>, <374 10>, <375 10>, <376 10>,
<377 10>, <378 10>, <379 10>, <380 10>,
<381 10>, <382 10>, <383 10>, <384 10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
gpio0: gpio@0 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x0>;
status = "disabled";
};
gpio1: gpio@100 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <6>;
reg = <0x100>;
status = "disabled";
};
gpio2: gpio@200 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <2>;
reg = <0x200>;
status = "disabled";
};
gpio3: gpio@300 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x300>;
status = "disabled";
};
gpio4: gpio@400 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x400>;
status = "disabled";
};
gpio5: gpio@500 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x500>;
status = "disabled";
};
gpio6: gpio@600 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x600>;
status = "disabled";
};
gpio7: gpio@700 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x700>;
status = "disabled";
};
gpio8: gpio@800 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x800>;
status = "disabled";
};
gpio9: gpio@900 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0x900>;
status = "disabled";
};
gpio10: gpio@a00 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0xa00>;
status = "disabled";
};
gpio11: gpio@b00 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <6>;
reg = <0xb00>;
status = "disabled";
};
};
};
sci0: sci0@42800c00 {