From 5599bc2ecb1dcc878d7e7e827937de301b702df0 Mon Sep 17 00:00:00 2001 From: Tien Nguyen Date: Tue, 10 Jun 2025 10:14:48 +0700 Subject: [PATCH] drivers: gpio: Add support for RZ/V2N Add support for RZ/V2N Signed-off-by: Tien Nguyen Signed-off-by: Hieu Nguyen --- drivers/gpio/gpio_renesas_rz.c | 2 +- drivers/gpio/gpio_renesas_rz.h | 5 +- dts/arm/renesas/rz/rzv/r9a09g056.dtsi | 124 ++++++++++++++++++++++++++ 3 files changed, 128 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio_renesas_rz.c b/drivers/gpio/gpio_renesas_rz.c index 25e9c8f728c..8d1351e5c2f 100644 --- a/drivers/gpio/gpio_renesas_rz.c +++ b/drivers/gpio/gpio_renesas_rz.c @@ -352,7 +352,7 @@ static int gpio_rz_int_enable(const struct device *gpio_int_dev, const struct de /* Select interrupt source base on port and pin number. */ *tssr &= ~(0xFF << (int_num)); *tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(int_num); - /* Select TINT source(only for RZV2H) */ + /* Select TINT source */ GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR(int_num); GPIO_RZ_TINT_SELECT_SOURCE_REG_SET(int_num); diff --git a/drivers/gpio/gpio_renesas_rz.h b/drivers/gpio/gpio_renesas_rz.h index d6554de4823..3258ca8bd06 100644 --- a/drivers/gpio/gpio_renesas_rz.h +++ b/drivers/gpio/gpio_renesas_rz.h @@ -14,7 +14,8 @@ #if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL) || \ defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L) || \ - defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZG2UL) + defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZG2UL) || \ + defined(CONFIG_SOC_SERIES_RZV2N) #include #if defined(CONFIG_SOC_SERIES_RZG3S) @@ -39,7 +40,7 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23 static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43, 47, 52, 56, 58, 63, 66, 70, 72, 76}; -#elif defined(CONFIG_SOC_SERIES_RZV2H) +#elif defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZV2N) #define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P20) #define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM20) #define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC20) diff --git a/dts/arm/renesas/rz/rzv/r9a09g056.dtsi b/dts/arm/renesas/rz/rzv/r9a09g056.dtsi index 91b94dea522..a474112e624 100644 --- a/dts/arm/renesas/rz/rzv/r9a09g056.dtsi +++ b/dts/arm/renesas/rz/rzv/r9a09g056.dtsi @@ -36,6 +36,130 @@ compatible = "renesas,rzv-pinctrl"; reg = <0x40410000 DT_SIZE_K(64)>; reg-names = "pinctrl"; + + gpio: gpio-common { + compatible = "renesas,rz-gpio-int"; + interrupts = + <353 10>, <354 10>, <355 10>, <356 10>, + <357 10>, <358 10>, <359 10>, <360 10>, + <361 10>, <362 10>, <363 10>, <364 10>, + <365 10>, <366 10>, <367 10>, <368 10>, + <369 10>, <370 10>, <371 10>, <372 10>, + <373 10>, <374 10>, <375 10>, <376 10>, + <377 10>, <378 10>, <379 10>, <380 10>, + <381 10>, <382 10>, <383 10>, <384 10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + gpio0: gpio@0 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x0>; + status = "disabled"; + }; + + gpio1: gpio@100 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <6>; + reg = <0x100>; + status = "disabled"; + }; + + gpio2: gpio@200 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <2>; + reg = <0x200>; + status = "disabled"; + }; + + gpio3: gpio@300 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x300>; + status = "disabled"; + }; + + gpio4: gpio@400 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x400>; + status = "disabled"; + }; + + gpio5: gpio@500 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x500>; + status = "disabled"; + }; + + gpio6: gpio@600 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x600>; + status = "disabled"; + }; + + gpio7: gpio@700 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x700>; + status = "disabled"; + }; + + gpio8: gpio@800 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x800>; + status = "disabled"; + }; + + gpio9: gpio@900 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x900>; + status = "disabled"; + }; + + gpio10: gpio@a00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0xa00>; + status = "disabled"; + }; + + gpio11: gpio@b00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <6>; + reg = <0xb00>; + status = "disabled"; + }; + }; }; sci0: sci0@42800c00 {