cmake: riscv: update riscv SoC to use SOC_LINKER_SCRIPT variable

This commit updates all riscv SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>

soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt

@@ -94,3 +94,9 @@ endif()
 board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}")
 
 board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
+
+if(CONFIG_MCUBOOT)
+  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
+else()
+  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
+endif()

soc/riscv/espressif_esp32/esp32c3/linker.ld

@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Linker command/script file
- *
- */
-
-#if defined(CONFIG_MCUBOOT)
-  /* Using mcuboot as ESP32C3 2nd stage bootloader */
-  #include "mcuboot.ld"
-
-#else
-  /* Application default linker script */
-  #include "default.ld"
-
-#endif /* CONFIG_MCUBOOT */

soc/riscv/litex-vexriscv/CMakeLists.txt

@@ -8,3 +8,5 @@ zephyr_sources(
     ../riscv-privileged/common/soc_irq.S
     ../riscv-privileged/common/vector.S
 )
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/riscv/litex-vexriscv/linker.ld

@@ -1,7 +0,0 @@
-/*
- * Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/arch/riscv/common/linker.ld>

soc/riscv/openisa_rv32m1/CMakeLists.txt

@@ -20,3 +20,5 @@ zephyr_sources(
 )
 
 zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-ite/it8xxx2/CMakeLists.txt

@@ -3,3 +3,7 @@ zephyr_sources(
 )
 zephyr_library_sources_ifndef(CONFIG_RISCV_ISA_EXT_M __arithmetic.S)
 zephyr_sources_ifdef(CONFIG_SOC_IT8XXX2_USE_ILM ilm.c)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld
+    CACHE INTERNAL "SoC Linker script ${SOC_NAME}"
+)

soc/riscv/riscv-privileged/andes_v5/CMakeLists.txt

@@ -23,3 +23,7 @@ if(CONFIG_SOC_ANDES_V5_EXECIT)
   zephyr_cc_option(-mexecit)
   zephyr_ld_options(-Wl,--mexecit)
 endif()
+
+if(CONFIG_SOC_RISCV_ANDES_AE350)
+  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/ae350/linker.ld CACHE INTERNAL "")
+endif()

soc/riscv/riscv-privileged/andes_v5/linker.ld

@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2021 Andes Technology Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Linker command/script file
- *
- * linker script for andes_v5 SoC Series
- */
-
-
-#if defined(CONFIG_SOC_RISCV_ANDES_AE350)
-# include <ae350/linker.ld>
-#endif

soc/riscv/riscv-privileged/efinix-sapphire/CMakeLists.txt

@@ -2,3 +2,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-privileged/efinix-sapphire/linker.ld

@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-#include <zephyr/arch/riscv/common/linker.ld>

soc/riscv/riscv-privileged/gd32vf103/CMakeLists.txt

@@ -3,3 +3,5 @@
 
 zephyr_sources(entry.S)
 zephyr_sources(soc.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-privileged/gd32vf103/linker.ld

@@ -1,7 +0,0 @@
-/*
- * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/arch/riscv/common/linker.ld>

soc/riscv/riscv-privileged/miv/CMakeLists.txt

@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_sources()
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-privileged/miv/linker.ld

@@ -1,7 +0,0 @@
-/*
- * Copyright (c) 2018 Antmicro <www.antmicro.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/arch/riscv/common/linker.ld>

soc/riscv/riscv-privileged/mpfs/CMakeLists.txt

@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_sources()
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-privileged/mpfs/linker.ld

@@ -1,7 +0,0 @@
-/*
- * Copyright (c) 2021-2022 Microchip Technology Inc
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/arch/riscv/common/linker.ld>

soc/riscv/riscv-privileged/neorv32/CMakeLists.txt

@@ -6,3 +6,5 @@ zephyr_sources(
   soc_irq.S
   soc.c
 )
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-privileged/niosv/CMakeLists.txt

@@ -2,3 +2,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-privileged/opentitan/CMakeLists.txt

@@ -3,3 +3,5 @@
 zephyr_sources(soc.c rom_header.S)
 
 zephyr_linker_sources(ROM_START SORT_KEY 000romheader rom_header.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-privileged/opentitan/linker.ld

@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: Apache-2.0 */
-
-#include <zephyr/arch/riscv/common/linker.ld>

soc/riscv/riscv-privileged/sifive-freedom/CMakeLists.txt

@@ -4,3 +4,5 @@ zephyr_sources()
 zephyr_sources_ifdef(CONFIG_SOC_RISCV_SIFIVE_FREEDOM fe310_clock.c)
 zephyr_sources_ifdef(CONFIG_SOC_RISCV_SIFIVE_FU540 fu540_clock.c)
 zephyr_sources_ifdef(CONFIG_SOC_RISCV_SIFIVE_FU740 fu740_clock.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-privileged/sifive-freedom/linker.ld

@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Linker script for the SiFive Freedom processor
- */
-
-#include <zephyr/arch/riscv/common/linker.ld>

soc/riscv/riscv-privileged/starfive_jh71xx/CMakeLists.txt

@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-privileged/starfive_jh71xx/linker.ld

@@ -1,6 +0,0 @@
-/*
- * Copyright (c) 2020 Cobham Gaisler AB
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <zephyr/arch/riscv/common/linker.ld>

soc/riscv/riscv-privileged/telink_b91/CMakeLists.txt

@@ -14,3 +14,5 @@ zephyr_ld_options(-fuse-ld=bfd)
 zephyr_compile_options_ifdef(CONFIG_TELINK_B91_HWDSP -mext-dsp)
 zephyr_compile_options_ifndef(CONFIG_RISCV_GP -mno-relax)
 zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-privileged/virt/CMakeLists.txt

@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_sources(soc.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/riscv/riscv-privileged/virt/linker.ld

@@ -1,6 +0,0 @@
-/*
- * Copyright (c) 2020 Cobham Gaisler AB
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <zephyr/arch/riscv/common/linker.ld>