From 10fea41f5cabef58cce0e6fcabccacbdec810798 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Fri, 27 Oct 2023 22:37:54 +0200 Subject: [PATCH] cmake: riscv: update riscv SoC to use SOC_LINKER_SCRIPT variable This commit updates all riscv SoCs to set SOC_LINKER_SCRIPT CMake variable to point to active linker script directly. Signed-off-by: Torsten Rasmussen --- .../espressif_esp32/esp32c3/CMakeLists.txt | 6 ++++++ soc/riscv/espressif_esp32/esp32c3/linker.ld | 20 ------------------- soc/riscv/litex-vexriscv/CMakeLists.txt | 2 ++ soc/riscv/litex-vexriscv/linker.ld | 7 ------- soc/riscv/openisa_rv32m1/CMakeLists.txt | 2 ++ soc/riscv/riscv-ite/it8xxx2/CMakeLists.txt | 4 ++++ .../riscv-privileged/andes_v5/CMakeLists.txt | 4 ++++ soc/riscv/riscv-privileged/andes_v5/linker.ld | 17 ---------------- .../efinix-sapphire/CMakeLists.txt | 2 ++ .../efinix-sapphire/linker.ld | 3 --- .../riscv-privileged/gd32vf103/CMakeLists.txt | 2 ++ .../riscv-privileged/gd32vf103/linker.ld | 7 ------- soc/riscv/riscv-privileged/miv/CMakeLists.txt | 2 ++ soc/riscv/riscv-privileged/miv/linker.ld | 7 ------- .../riscv-privileged/mpfs/CMakeLists.txt | 2 ++ soc/riscv/riscv-privileged/mpfs/linker.ld | 7 ------- .../riscv-privileged/neorv32/CMakeLists.txt | 2 ++ .../riscv-privileged/niosv/CMakeLists.txt | 2 ++ .../riscv-privileged/opentitan/CMakeLists.txt | 2 ++ .../riscv-privileged/opentitan/linker.ld | 3 --- .../sifive-freedom/CMakeLists.txt | 2 ++ .../riscv-privileged/sifive-freedom/linker.ld | 11 ---------- .../starfive_jh71xx/CMakeLists.txt | 2 ++ .../starfive_jh71xx/linker.ld | 6 ------ .../telink_b91/CMakeLists.txt | 2 ++ .../riscv-privileged/virt/CMakeLists.txt | 2 ++ soc/riscv/riscv-privileged/virt/linker.ld | 6 ------ 27 files changed, 40 insertions(+), 94 deletions(-) delete mode 100644 soc/riscv/espressif_esp32/esp32c3/linker.ld delete mode 100644 soc/riscv/litex-vexriscv/linker.ld delete mode 100644 soc/riscv/riscv-privileged/andes_v5/linker.ld delete mode 100644 soc/riscv/riscv-privileged/efinix-sapphire/linker.ld delete mode 100644 soc/riscv/riscv-privileged/gd32vf103/linker.ld delete mode 100644 soc/riscv/riscv-privileged/miv/linker.ld delete mode 100644 soc/riscv/riscv-privileged/mpfs/linker.ld delete mode 100644 soc/riscv/riscv-privileged/opentitan/linker.ld delete mode 100644 soc/riscv/riscv-privileged/sifive-freedom/linker.ld delete mode 100644 soc/riscv/riscv-privileged/starfive_jh71xx/linker.ld delete mode 100644 soc/riscv/riscv-privileged/virt/linker.ld diff --git a/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt b/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt index 4dd457b6801..e97f71751ef 100644 --- a/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt +++ b/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt @@ -94,3 +94,9 @@ endif() board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + +if(CONFIG_MCUBOOT) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") +else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") +endif() diff --git a/soc/riscv/espressif_esp32/esp32c3/linker.ld b/soc/riscv/espressif_esp32/esp32c3/linker.ld deleted file mode 100644 index 934088ca728..00000000000 --- a/soc/riscv/espressif_esp32/esp32c3/linker.ld +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - */ - -#if defined(CONFIG_MCUBOOT) - /* Using mcuboot as ESP32C3 2nd stage bootloader */ - #include "mcuboot.ld" - -#else - /* Application default linker script */ - #include "default.ld" - -#endif /* CONFIG_MCUBOOT */ diff --git a/soc/riscv/litex-vexriscv/CMakeLists.txt b/soc/riscv/litex-vexriscv/CMakeLists.txt index 34d6046ab68..9d100ea0e2a 100644 --- a/soc/riscv/litex-vexriscv/CMakeLists.txt +++ b/soc/riscv/litex-vexriscv/CMakeLists.txt @@ -8,3 +8,5 @@ zephyr_sources( ../riscv-privileged/common/soc_irq.S ../riscv-privileged/common/vector.S ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/litex-vexriscv/linker.ld b/soc/riscv/litex-vexriscv/linker.ld deleted file mode 100644 index 424ee50014f..00000000000 --- a/soc/riscv/litex-vexriscv/linker.ld +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2018 - 2019 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include diff --git a/soc/riscv/openisa_rv32m1/CMakeLists.txt b/soc/riscv/openisa_rv32m1/CMakeLists.txt index 37f4d9c7488..a7a722279c3 100644 --- a/soc/riscv/openisa_rv32m1/CMakeLists.txt +++ b/soc/riscv/openisa_rv32m1/CMakeLists.txt @@ -20,3 +20,5 @@ zephyr_sources( ) zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-ite/it8xxx2/CMakeLists.txt b/soc/riscv/riscv-ite/it8xxx2/CMakeLists.txt index b7eff43b096..df4d9021745 100644 --- a/soc/riscv/riscv-ite/it8xxx2/CMakeLists.txt +++ b/soc/riscv/riscv-ite/it8xxx2/CMakeLists.txt @@ -3,3 +3,7 @@ zephyr_sources( ) zephyr_library_sources_ifndef(CONFIG_RISCV_ISA_EXT_M __arithmetic.S) zephyr_sources_ifdef(CONFIG_SOC_IT8XXX2_USE_ILM ilm.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld + CACHE INTERNAL "SoC Linker script ${SOC_NAME}" +) diff --git a/soc/riscv/riscv-privileged/andes_v5/CMakeLists.txt b/soc/riscv/riscv-privileged/andes_v5/CMakeLists.txt index 3de7b8c8841..21268312347 100644 --- a/soc/riscv/riscv-privileged/andes_v5/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/andes_v5/CMakeLists.txt @@ -23,3 +23,7 @@ if(CONFIG_SOC_ANDES_V5_EXECIT) zephyr_cc_option(-mexecit) zephyr_ld_options(-Wl,--mexecit) endif() + +if(CONFIG_SOC_RISCV_ANDES_AE350) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/ae350/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/riscv/riscv-privileged/andes_v5/linker.ld b/soc/riscv/riscv-privileged/andes_v5/linker.ld deleted file mode 100644 index 5f92edc75a9..00000000000 --- a/soc/riscv/riscv-privileged/andes_v5/linker.ld +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2021 Andes Technology Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * linker script for andes_v5 SoC Series - */ - - -#if defined(CONFIG_SOC_RISCV_ANDES_AE350) -# include -#endif diff --git a/soc/riscv/riscv-privileged/efinix-sapphire/CMakeLists.txt b/soc/riscv/riscv-privileged/efinix-sapphire/CMakeLists.txt index 9fc80635937..9edb7c3afe5 100644 --- a/soc/riscv/riscv-privileged/efinix-sapphire/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/efinix-sapphire/CMakeLists.txt @@ -2,3 +2,5 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-privileged/efinix-sapphire/linker.ld b/soc/riscv/riscv-privileged/efinix-sapphire/linker.ld deleted file mode 100644 index 4cfd67a53f5..00000000000 --- a/soc/riscv/riscv-privileged/efinix-sapphire/linker.ld +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -#include diff --git a/soc/riscv/riscv-privileged/gd32vf103/CMakeLists.txt b/soc/riscv/riscv-privileged/gd32vf103/CMakeLists.txt index a3cabd57ab1..be61e4a64df 100644 --- a/soc/riscv/riscv-privileged/gd32vf103/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/gd32vf103/CMakeLists.txt @@ -3,3 +3,5 @@ zephyr_sources(entry.S) zephyr_sources(soc.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-privileged/gd32vf103/linker.ld b/soc/riscv/riscv-privileged/gd32vf103/linker.ld deleted file mode 100644 index 849c94ebe96..00000000000 --- a/soc/riscv/riscv-privileged/gd32vf103/linker.ld +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2021 Tokita, Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include diff --git a/soc/riscv/riscv-privileged/miv/CMakeLists.txt b/soc/riscv/riscv-privileged/miv/CMakeLists.txt index 55fc3999fd7..316f08474ba 100644 --- a/soc/riscv/riscv-privileged/miv/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/miv/CMakeLists.txt @@ -1,3 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_sources() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-privileged/miv/linker.ld b/soc/riscv/riscv-privileged/miv/linker.ld deleted file mode 100644 index 0d220a25c73..00000000000 --- a/soc/riscv/riscv-privileged/miv/linker.ld +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2018 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include diff --git a/soc/riscv/riscv-privileged/mpfs/CMakeLists.txt b/soc/riscv/riscv-privileged/mpfs/CMakeLists.txt index 55fc3999fd7..316f08474ba 100644 --- a/soc/riscv/riscv-privileged/mpfs/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/mpfs/CMakeLists.txt @@ -1,3 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_sources() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-privileged/mpfs/linker.ld b/soc/riscv/riscv-privileged/mpfs/linker.ld deleted file mode 100644 index 4e3ca81bfbb..00000000000 --- a/soc/riscv/riscv-privileged/mpfs/linker.ld +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2021-2022 Microchip Technology Inc - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include diff --git a/soc/riscv/riscv-privileged/neorv32/CMakeLists.txt b/soc/riscv/riscv-privileged/neorv32/CMakeLists.txt index 7f7c334fedd..42731316d84 100644 --- a/soc/riscv/riscv-privileged/neorv32/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/neorv32/CMakeLists.txt @@ -6,3 +6,5 @@ zephyr_sources( soc_irq.S soc.c ) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-privileged/niosv/CMakeLists.txt b/soc/riscv/riscv-privileged/niosv/CMakeLists.txt index c740850bc77..e7a753a2db3 100644 --- a/soc/riscv/riscv-privileged/niosv/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/niosv/CMakeLists.txt @@ -2,3 +2,5 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-privileged/opentitan/CMakeLists.txt b/soc/riscv/riscv-privileged/opentitan/CMakeLists.txt index 05e59ca7071..3502022cbed 100644 --- a/soc/riscv/riscv-privileged/opentitan/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/opentitan/CMakeLists.txt @@ -3,3 +3,5 @@ zephyr_sources(soc.c rom_header.S) zephyr_linker_sources(ROM_START SORT_KEY 000romheader rom_header.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-privileged/opentitan/linker.ld b/soc/riscv/riscv-privileged/opentitan/linker.ld deleted file mode 100644 index 8eeb9c50af3..00000000000 --- a/soc/riscv/riscv-privileged/opentitan/linker.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include diff --git a/soc/riscv/riscv-privileged/sifive-freedom/CMakeLists.txt b/soc/riscv/riscv-privileged/sifive-freedom/CMakeLists.txt index f5f6c539efd..ff4cc56d739 100644 --- a/soc/riscv/riscv-privileged/sifive-freedom/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/sifive-freedom/CMakeLists.txt @@ -4,3 +4,5 @@ zephyr_sources() zephyr_sources_ifdef(CONFIG_SOC_RISCV_SIFIVE_FREEDOM fe310_clock.c) zephyr_sources_ifdef(CONFIG_SOC_RISCV_SIFIVE_FU540 fu540_clock.c) zephyr_sources_ifdef(CONFIG_SOC_RISCV_SIFIVE_FU740 fu740_clock.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-privileged/sifive-freedom/linker.ld b/soc/riscv/riscv-privileged/sifive-freedom/linker.ld deleted file mode 100644 index 96720f18a2e..00000000000 --- a/soc/riscv/riscv-privileged/sifive-freedom/linker.ld +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2017 Jean-Paul Etienne - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @brief Linker script for the SiFive Freedom processor - */ - -#include diff --git a/soc/riscv/riscv-privileged/starfive_jh71xx/CMakeLists.txt b/soc/riscv/riscv-privileged/starfive_jh71xx/CMakeLists.txt index f75aec6b311..f79d0b3255d 100644 --- a/soc/riscv/riscv-privileged/starfive_jh71xx/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/starfive_jh71xx/CMakeLists.txt @@ -1,3 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-privileged/starfive_jh71xx/linker.ld b/soc/riscv/riscv-privileged/starfive_jh71xx/linker.ld deleted file mode 100644 index 4e63d62344d..00000000000 --- a/soc/riscv/riscv-privileged/starfive_jh71xx/linker.ld +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2020 Cobham Gaisler AB - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include diff --git a/soc/riscv/riscv-privileged/telink_b91/CMakeLists.txt b/soc/riscv/riscv-privileged/telink_b91/CMakeLists.txt index c91adf6a993..8c489ac6dd7 100644 --- a/soc/riscv/riscv-privileged/telink_b91/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/telink_b91/CMakeLists.txt @@ -14,3 +14,5 @@ zephyr_ld_options(-fuse-ld=bfd) zephyr_compile_options_ifdef(CONFIG_TELINK_B91_HWDSP -mext-dsp) zephyr_compile_options_ifndef(CONFIG_RISCV_GP -mno-relax) zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-privileged/virt/CMakeLists.txt b/soc/riscv/riscv-privileged/virt/CMakeLists.txt index 9486f255912..6a1826b29f9 100644 --- a/soc/riscv/riscv-privileged/virt/CMakeLists.txt +++ b/soc/riscv/riscv-privileged/virt/CMakeLists.txt @@ -1,3 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_sources(soc.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/riscv-privileged/virt/linker.ld b/soc/riscv/riscv-privileged/virt/linker.ld deleted file mode 100644 index 4e63d62344d..00000000000 --- a/soc/riscv/riscv-privileged/virt/linker.ld +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2020 Cobham Gaisler AB - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include