Flavio Ceolin 86b87ae42d samples: sof: Uses CONFIG_SCHED_CPU_MASK_PIN_ONLY ... SoF pins threads to specific cores and don't need them to be executed in multiple cores. This options allows Zephyr to do cache optimizations during context switches. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>		2022-08-29 11:39:02 +02:00
..
canopennode	samples: canopenmode exclude nvs_sector_size above 64K	2022-07-13 10:14:03 +02:00
chre	samples: migrate includes to contain <zephyr/...> prefix	2022-05-06 11:29:59 +02:00
nanopb	samples: modules: nanopb: Limit the integration platforms	2022-07-29 13:35:48 -04:00
sof	samples: sof: Uses CONFIG_SCHED_CPU_MASK_PIN_ONLY	2022-08-29 11:39:02 +02:00
tflite-micro	devices: constify device pointers initialized at compile time	2022-08-22 17:08:26 +02:00
index.rst