ffe6910e21
Add dedicated interrupt lines for nrf54h20_cpuppr. Similar exception
was already added to nrf54l15_flpr: 8742e2476.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
174 lines
4.4 KiB
C
174 lines
4.4 KiB
C
/*
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* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/ztest.h>
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#include <zephyr/interrupt_util.h>
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/*
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* Run the nested interrupt test for the supported platforms only.
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*/
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#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_ARC) || \
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defined(CONFIG_GIC) || defined(CONFIG_NRFX_CLIC)
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#define TEST_NESTED_ISR
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#endif
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#define DURATION 5
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#define ISR0_TOKEN 0xDEADBEEF
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#define ISR1_TOKEN 0xCAFEBABE
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/*
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* This test uses two IRQ lines selected within the range of available IRQs on
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* the target SoC. These IRQs are platform and interrupt controller-specific,
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* and must be specified for every supported platform.
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*
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* In terms of priority, the IRQ1 is triggered from the ISR of the IRQ0;
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* therefore, the priority of IRQ1 must be greater than that of the IRQ0.
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*/
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#if defined(CONFIG_CPU_CORTEX_M)
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/*
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* For Cortex-M NVIC, unused and available IRQs are automatically detected when
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* the test is run.
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*
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* The IRQ priorities start at 1 because the priority 0 is reserved for the
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* SVCall exception and Zero-Latency IRQs (see `_EXCEPTION_RESERVED_PRIO`).
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*/
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#define IRQ0_PRIO 2
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#define IRQ1_PRIO 1
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#elif defined(CONFIG_GIC)
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/*
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* For the platforms that use the ARM GIC, use the SGI (software generated
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* interrupt) lines 14 and 15 for testing.
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*/
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#define IRQ0_LINE 14
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#define IRQ1_LINE 15
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/*
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* Choose lower prio for IRQ0 and higher priority for IRQ1
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* Minimum legal value of GICC BPR is '3' ie <gggg.ssss>
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* Hence choosing default priority and highest possible priority
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* '0x0' as the priorities so that the preemption rule applies
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* generically to all GIC versions and security states.
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*/
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#define IRQ0_PRIO IRQ_DEFAULT_PRIORITY
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#define IRQ1_PRIO 0x0
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#elif defined(CONFIG_SOC_NRF54L15_ENGA_CPUFLPR) || defined(CONFIG_SOC_NRF54L15_CPUFLPR)
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#define IRQ0_LINE 16
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#define IRQ1_LINE 17
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#define IRQ0_PRIO 1
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#define IRQ1_PRIO 2
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#elif defined(CONFIG_SOC_NRF54H20_CPUPPR)
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#define IRQ0_LINE 14
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#define IRQ1_LINE 15
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#define IRQ0_PRIO 1
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#define IRQ1_PRIO 2
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#else
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/*
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* For all the other platforms, use the last two available IRQ lines for
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* testing.
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*/
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#define IRQ0_LINE (CONFIG_NUM_IRQS - 1)
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#define IRQ1_LINE (CONFIG_NUM_IRQS - 2)
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#define IRQ0_PRIO 1
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#define IRQ1_PRIO 0
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#endif
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#ifdef TEST_NESTED_ISR
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static uint32_t irq_line_0;
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static uint32_t irq_line_1;
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static uint32_t isr0_result;
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static uint32_t isr1_result;
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void isr1(const void *param)
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{
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ARG_UNUSED(param);
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printk("isr1: Enter\n");
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/* Set verification token */
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isr1_result = ISR1_TOKEN;
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printk("isr1: Leave\n");
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}
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void isr0(const void *param)
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{
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ARG_UNUSED(param);
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printk("isr0: Enter\n");
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/* Set verification token */
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isr0_result = ISR0_TOKEN;
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/* Trigger nested IRQ 1 */
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trigger_irq(irq_line_1);
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/* Wait for interrupt */
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k_busy_wait(MS_TO_US(DURATION));
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/* Validate nested ISR result token */
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zassert_equal(isr1_result, ISR1_TOKEN, "isr1 did not execute");
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printk("isr0: Leave\n");
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}
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/**
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* @brief Test interrupt nesting
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*
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* @ingroup kernel_interrupt_tests
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*
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* This routine tests the interrupt nesting feature, which allows an ISR to be
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* preempted in mid-execution if a higher priority interrupt is signaled. The
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* lower priority ISR resumes execution once the higher priority ISR has
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* completed its processing.
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*
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* The expected control flow for this test is as follows:
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*
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* 1. [thread] Trigger IRQ 0 (lower priority)
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* 2. [isr0] Set ISR 0 result token and trigger IRQ 1 (higher priority)
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* 3. [isr1] Set ISR 1 result token and return
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* 4. [isr0] Validate ISR 1 result token and return
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* 5. [thread] Validate ISR 0 result token
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*/
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ZTEST(interrupt_feature, test_nested_isr)
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{
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/* Resolve test IRQ line numbers */
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#if defined(CONFIG_CPU_CORTEX_M)
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irq_line_0 = get_available_nvic_line(CONFIG_NUM_IRQS);
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irq_line_1 = get_available_nvic_line(irq_line_0);
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#else
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irq_line_0 = IRQ0_LINE;
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irq_line_1 = IRQ1_LINE;
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#endif
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/* Connect and enable test IRQs */
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arch_irq_connect_dynamic(irq_line_0, IRQ0_PRIO, isr0, NULL, 0);
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arch_irq_connect_dynamic(irq_line_1, IRQ1_PRIO, isr1, NULL, 0);
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irq_enable(irq_line_0);
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irq_enable(irq_line_1);
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/* Trigger test IRQ 0 */
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trigger_irq(irq_line_0);
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/* Wait for interrupt */
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k_busy_wait(MS_TO_US(DURATION));
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/* Validate ISR result token */
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zassert_equal(isr0_result, ISR0_TOKEN, "isr0 did not execute");
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}
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#else
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ZTEST(interrupt_feature, test_nested_isr)
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{
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ztest_test_skip();
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}
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#endif /* TEST_NESTED_ISR */
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